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i965: Make brw_update_sampler_state use 8 bits for LOD fields on Gen7+.

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This was the only actual difference between Gen4-6 and Gen7+ in terms of
the values we program.  The rest was just mechanical structure
rearrangement.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
Kenneth Graunke 2014-07-26 13:12:37 -07:00
parent a50b640dfe
commit 7679393f56
1 changed files with 4 additions and 3 deletions
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7
src/mesa/drivers/dri/i965/brw_sampler_state.c
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@ -424,10 +424,11 @@ brw_update_sampler_state(struct brw_context *brw,
intel_translate_shadow_compare_func(sampler->CompareFunc);
}
const unsigned min_lod = U_FIXED(CLAMP(sampler->MinLod, 0, 13), 6);
const unsigned max_lod = U_FIXED(CLAMP(sampler->MaxLod, 0, 13), 6);
const int lod_bits = brw->gen >= 7 ? 8 : 6;
const unsigned min_lod = U_FIXED(CLAMP(sampler->MinLod, 0, 13), lod_bits);
const unsigned max_lod = U_FIXED(CLAMP(sampler->MaxLod, 0, 13), lod_bits);
const int lod_bias =
S_FIXED(CLAMP(texUnit->LodBias + sampler->LodBias, -16, 15), 6);
S_FIXED(CLAMP(texUnit->LodBias + sampler->LodBias, -16, 15), lod_bits);
const unsigned base_level = U_FIXED(0, 1);
uint32_t border_color_offset;