fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-21 22:20:14 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

i965/gs: Add GS_OPCODE_SET_VERTEX_COUNT.

Browse source 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Paul Berry 2013-03-23 08:18:43 -07:00
parent ce722fd65d
commit 7417eddea9
4 changed files with 45 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
src/mesa/drivers/dri/i965/brw_defines.h
View file

@ -833,6 +833,16 @@ enum opcode {
* vec4_instruction::offset.
*/
GS_OPCODE_SET_WRITE_OFFSET,
/**
* Set the "GS Number of Output Vertices for Slot {0,1}" fields of a
* URB_WRITE message header.
*
* - dst is the MRF containing the message header.
*
* - src0.x is the vertex count. The upper 16 bits will be ignored.
*/
GS_OPCODE_SET_VERTEX_COUNT,
};
#define BRW_PREDICATE_NONE 0

2
src/mesa/drivers/dri/i965/brw_shader.cpp
View file

@ -503,6 +503,8 @@ brw_instruction_name(enum opcode op)
return "gs_thread_end";
case GS_OPCODE_SET_WRITE_OFFSET:
return "set_write_offset";
case GS_OPCODE_SET_VERTEX_COUNT:
return "set_vertex_count";
default:
/* Yes, this leaks. It's in debug code, it should never occur, and if

2
src/mesa/drivers/dri/i965/brw_vec4.h
View file

@ -633,6 +633,8 @@ private:
void generate_gs_set_write_offset(struct brw_reg dst,
struct brw_reg src0,
struct brw_reg src1);
void generate_gs_set_vertex_count(struct brw_reg dst,
struct brw_reg src);
void generate_oword_dual_block_offsets(struct brw_reg m1,
struct brw_reg index);
void generate_scratch_write(vec4_instruction *inst,

31
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
View file

@ -474,6 +474,33 @@ vec4_generator::generate_gs_set_write_offset(struct brw_reg dst,
brw_pop_insn_state(p);
}
void
vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst,
struct brw_reg src)
{
brw_push_insn_state(p);
brw_set_access_mode(p, BRW_ALIGN_1);
brw_set_mask_control(p, BRW_MASK_DISABLE);
/* If we think of the src and dst registers as composed of 8 DWORDs each,
* we want to pick up the contents of DWORDs 0 and 4 from src, truncate
* them to WORDs, and then pack them into DWORD 2 of dst.
*
* It's easier to get the EU to do this if we think of the src and dst
* registers as composed of 16 WORDS each; then, we want to pick up the
* contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5 of
* dst.
*
* We can do that by the following EU instruction:
*
* mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
*/
brw_MOV(p, suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
brw_set_access_mode(p, BRW_ALIGN_16);
brw_pop_insn_state(p);
}
void
vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
struct brw_reg index)
@ -954,6 +981,10 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
generate_gs_set_write_offset(dst, src[0], src[1]);
break;
case GS_OPCODE_SET_VERTEX_COUNT:
generate_gs_set_vertex_count(dst, src[0]);
break;
case SHADER_OPCODE_SHADER_TIME_ADD:
brw_shader_time_add(p, src[0], SURF_INDEX_VS_SHADER_TIME);
mark_surface_used(SURF_INDEX_VS_SHADER_TIME);