fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-07 11:28:05 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 4

brw: wire up MACL

Browse source 
New on Xe2, this instruction enables faster 32x32 integer multiply at the cost
of extra accumulator usage. Add it to the opcode list for future use.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40833>
This commit is contained in:
Alyssa Rosenzweig 2025-12-11 12:38:48 -05:00 • committed by Marge Bot
parent 01516746eb
commit 73701c305e
4 changed files with 4 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/intel/compiler/brw/brw_eu.c
View file

@ -618,6 +618,7 @@ static const struct opcode_desc opcode_descs[] = {
{ BRW_OPCODE_ADDC, 78, "addc", 2, 1, GFX_ALL },
{ BRW_OPCODE_SUBB, 79, "subb", 2, 1, GFX_ALL },
{ BRW_OPCODE_ADD3, 82, "add3", 3, 1, GFX_GE(GFX125) },
{ BRW_OPCODE_MACL, 83, "macl", 2, 1, GFX_GE(XE2) },
{ BRW_OPCODE_DP4, 84, "dp4", 2, 1, GFX_LT(GFX11) },
{ BRW_OPCODE_SRND, 84, "srnd", 2, 1, GFX_GE(XE2) },
{ BRW_OPCODE_DPH, 85, "dph", 2, 1, GFX_LT(GFX11) },

1
src/intel/compiler/brw/brw_eu.h
View file

@ -205,6 +205,7 @@ ALU1(RNDE)
ALU1(RNDU)
ALU1(RNDZ)
ALU2(MAC)
ALU2(MACL)
ALU2(MACH)
ALU1(LZD)
ALU2(DP4)

1
src/intel/compiler/brw/brw_eu_defines.h
View file

@ -187,6 +187,7 @@ enum ENUM_PACKED opcode {
BRW_OPCODE_RNDE,
BRW_OPCODE_RNDZ,
BRW_OPCODE_MAC,
BRW_OPCODE_MACL,
BRW_OPCODE_MACH,
BRW_OPCODE_LZD,
BRW_OPCODE_FBH,

1
src/intel/compiler/brw/brw_eu_emit.c
View file

@ -843,6 +843,7 @@ ALU1(RNDE)
ALU1(RNDU)
ALU1(RNDZ)
ALU2(MAC)
ALU2(MACL)
ALU2(MACH)
ALU1(LZD)
ALU2(DP4)