From 73701c305e9ddc4087a3f68a372193a841cebed9 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Thu, 11 Dec 2025 12:38:48 -0500 Subject: [PATCH] brw: wire up MACL New on Xe2, this instruction enables faster 32x32 integer multiply at the cost of extra accumulator usage. Add it to the opcode list for future use. Signed-off-by: Alyssa Rosenzweig Reviewed-by: Kenneth Graunke Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/compiler/brw/brw_eu.c | 1 + src/intel/compiler/brw/brw_eu.h | 1 + src/intel/compiler/brw/brw_eu_defines.h | 1 + src/intel/compiler/brw/brw_eu_emit.c | 1 + 4 files changed, 4 insertions(+) diff --git a/src/intel/compiler/brw/brw_eu.c b/src/intel/compiler/brw/brw_eu.c index 6d644bd01db..29e7aa2a53e 100644 --- a/src/intel/compiler/brw/brw_eu.c +++ b/src/intel/compiler/brw/brw_eu.c @@ -618,6 +618,7 @@ static const struct opcode_desc opcode_descs[] = { { BRW_OPCODE_ADDC, 78, "addc", 2, 1, GFX_ALL }, { BRW_OPCODE_SUBB, 79, "subb", 2, 1, GFX_ALL }, { BRW_OPCODE_ADD3, 82, "add3", 3, 1, GFX_GE(GFX125) }, + { BRW_OPCODE_MACL, 83, "macl", 2, 1, GFX_GE(XE2) }, { BRW_OPCODE_DP4, 84, "dp4", 2, 1, GFX_LT(GFX11) }, { BRW_OPCODE_SRND, 84, "srnd", 2, 1, GFX_GE(XE2) }, { BRW_OPCODE_DPH, 85, "dph", 2, 1, GFX_LT(GFX11) }, diff --git a/src/intel/compiler/brw/brw_eu.h b/src/intel/compiler/brw/brw_eu.h index 655574367d6..e44ce4ad9bb 100644 --- a/src/intel/compiler/brw/brw_eu.h +++ b/src/intel/compiler/brw/brw_eu.h @@ -205,6 +205,7 @@ ALU1(RNDE) ALU1(RNDU) ALU1(RNDZ) ALU2(MAC) +ALU2(MACL) ALU2(MACH) ALU1(LZD) ALU2(DP4) diff --git a/src/intel/compiler/brw/brw_eu_defines.h b/src/intel/compiler/brw/brw_eu_defines.h index cb2797e4d23..29801caa6de 100644 --- a/src/intel/compiler/brw/brw_eu_defines.h +++ b/src/intel/compiler/brw/brw_eu_defines.h @@ -187,6 +187,7 @@ enum ENUM_PACKED opcode { BRW_OPCODE_RNDE, BRW_OPCODE_RNDZ, BRW_OPCODE_MAC, + BRW_OPCODE_MACL, BRW_OPCODE_MACH, BRW_OPCODE_LZD, BRW_OPCODE_FBH, diff --git a/src/intel/compiler/brw/brw_eu_emit.c b/src/intel/compiler/brw/brw_eu_emit.c index b19a3925b3b..364fa667716 100644 --- a/src/intel/compiler/brw/brw_eu_emit.c +++ b/src/intel/compiler/brw/brw_eu_emit.c @@ -843,6 +843,7 @@ ALU1(RNDE) ALU1(RNDU) ALU1(RNDZ) ALU2(MAC) +ALU2(MACL) ALU2(MACH) ALU1(LZD) ALU2(DP4)