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radv: memset the alignment hole in cache_entry to 0

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Detected using valgrind. Otherwise these bytes at the end
will be touched by zstd compression, spamming valgrind output.

Other option is to do full memset(entry, 0, size),
but that is somehow unnecessary and suboptimal.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8229>
This commit is contained in:
Witold Baryluk 2021-01-28 17:52:06 +00:00 • committed by Marge Bot
parent 5fc5d18aac
commit 736834931b
1 changed files with 7 additions and 2 deletions
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9
src/amd/vulkan/radv_pipeline_cache.c
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@ -393,8 +393,8 @@ radv_pipeline_cache_insert_shaders(struct radv_device *device,
for (int i = 0; i < MESA_SHADER_STAGES; ++i)
if (variants[i])
size += binaries[i]->total_size;
size = align(size, alignof(struct cache_entry));
const size_t size_without_align = size;
size = align(size_without_align, alignof(struct cache_entry));
entry = vk_alloc(&cache->alloc, size, 8,
VK_SYSTEM_ALLOCATION_SCOPE_CACHE);
@ -418,6 +418,11 @@ radv_pipeline_cache_insert_shaders(struct radv_device *device,
p += binaries[i]->total_size;
}
// Make valgrind happy by filling the alignment hole at the end.
assert((void*)p == (void*)entry + size_without_align);
assert(sizeof(*entry) + ((void*)p - (void*)entry->code) == size_without_align);
memset((void*)entry + size_without_align, 0, size - size_without_align);
/* Always add cache items to disk. This will allow collection of
* compiled shaders by third parties such as steam, even if the app
* implements its own pipeline cache.