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brw: better model READ_ARF_REG opcode

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This opcode gets translated to 2 ALU instructions with dependency ALU
stall. This change reproduces the FS_OPCODE_PACK_HALF_2x16_SPLIT
values which is another opcode that generates 2 instructions.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29446>
This commit is contained in:
Lionel Landwerlin 2024-05-29 17:50:13 +03:00 • committed by Marge Bot
parent ac03cefb28
commit 724bb7fa15
1 changed files with 9 additions and 1 deletions
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10
src/intel/compiler/brw_ir_performance.cpp
View file

@ -312,7 +312,6 @@ namespace {
case FS_OPCODE_DDY_COARSE:
case FS_OPCODE_PIXEL_X:
case FS_OPCODE_PIXEL_Y:
case SHADER_OPCODE_READ_ARCH_REG:
if (devinfo->ver >= 11) {
return calculate_desc(info, EU_UNIT_FPU, 0, 2, 0, 0, 2,
0, 10, 6 /* XXX */, 14, 0, 0);
@ -457,6 +456,15 @@ namespace {
0, 8 /* XXX */, 4 /* XXX */,
12 /* XXX */, 0, 0);
case SHADER_OPCODE_READ_ARCH_REG:
if (devinfo->ver >= 12) {
return calculate_desc(info, EU_UNIT_FPU, 20, 6, 0, 0, 6,
0, 10, 6 /* XXX */, 14, 0, 0);
} else {
return calculate_desc(info, EU_UNIT_FPU, 0, 2, 0, 0, 2,
0, 8, 4, 12, 0, 0);
}
case SHADER_OPCODE_MOV_INDIRECT:
if (devinfo->ver >= 11)
return calculate_desc(info, EU_UNIT_FPU, 34, 0, 0, 34, 0,