From 724bb7fa151c420a32937736a84145da688a0a0d Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Wed, 29 May 2024 17:50:13 +0300 Subject: [PATCH] brw: better model READ_ARF_REG opcode This opcode gets translated to 2 ALU instructions with dependency ALU stall. This change reproduces the FS_OPCODE_PACK_HALF_2x16_SPLIT values which is another opcode that generates 2 instructions. Signed-off-by: Lionel Landwerlin Reviewed-by: Kenneth Graunke Part-of: --- src/intel/compiler/brw_ir_performance.cpp | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_ir_performance.cpp b/src/intel/compiler/brw_ir_performance.cpp index dec164cf3d7..a4539f088a6 100644 --- a/src/intel/compiler/brw_ir_performance.cpp +++ b/src/intel/compiler/brw_ir_performance.cpp @@ -312,7 +312,6 @@ namespace { case FS_OPCODE_DDY_COARSE: case FS_OPCODE_PIXEL_X: case FS_OPCODE_PIXEL_Y: - case SHADER_OPCODE_READ_ARCH_REG: if (devinfo->ver >= 11) { return calculate_desc(info, EU_UNIT_FPU, 0, 2, 0, 0, 2, 0, 10, 6 /* XXX */, 14, 0, 0); @@ -457,6 +456,15 @@ namespace { 0, 8 /* XXX */, 4 /* XXX */, 12 /* XXX */, 0, 0); + case SHADER_OPCODE_READ_ARCH_REG: + if (devinfo->ver >= 12) { + return calculate_desc(info, EU_UNIT_FPU, 20, 6, 0, 0, 6, + 0, 10, 6 /* XXX */, 14, 0, 0); + } else { + return calculate_desc(info, EU_UNIT_FPU, 0, 2, 0, 0, 2, + 0, 8, 4, 12, 0, 0); + } + case SHADER_OPCODE_MOV_INDIRECT: if (devinfo->ver >= 11) return calculate_desc(info, EU_UNIT_FPU, 34, 0, 0, 34, 0,