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tu: Fix CP_BLIT sync on A7XX

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A7XX needs the CCU blit caches to be flushed before a CP_BLIT to
ensure any writes from a CP_EVENT_WRITE::BLIT have landed, without
this the source buffer may have an incomplete load/clear when the
2D blit starts resulting in what's written out being broken.

The corruption can be seen with GMEM passes using CP_BLIT especially
when forced using `TU_DEBUG=gmem,unaligned_store`.

Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26461>
This commit is contained in:
Mark Collins 2024-01-23 01:51:56 +00:00 • committed by Marge Bot
parent 9a67f00398
commit 71918f7cff
1 changed files with 6 additions and 1 deletions
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7
src/freedreno/vulkan/tu_clear_blit.cc
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@ -3747,8 +3747,13 @@ store_cp_blit(struct tu_cmd_buffer *cmd,
/* sync GMEM writes with CACHE. */
tu_emit_event_write<CHIP>(cmd, cs, FD_CACHE_INVALIDATE);
if (CHIP >= A7XX)
/* On A7XX, we need to wait for any CP_EVENT_WRITE::BLIT operations
* arising from GMEM load/clears to land before we can continue.
*/
tu_emit_event_write<CHIP>(cmd, cs, FD_CCU_FLUSH_BLIT_CACHE);
/* Wait for CACHE_INVALIDATE to land */
/* Wait for cache event to land */
tu_cs_emit_wfi(cs);
r2d_run(cmd, cs);