From 71918f7cffc06b0a680440209b0547012b615af2 Mon Sep 17 00:00:00 2001 From: Mark Collins Date: Tue, 23 Jan 2024 01:51:56 +0000 Subject: [PATCH] tu: Fix CP_BLIT sync on A7XX A7XX needs the CCU blit caches to be flushed before a CP_BLIT to ensure any writes from a CP_EVENT_WRITE::BLIT have landed, without this the source buffer may have an incomplete load/clear when the 2D blit starts resulting in what's written out being broken. The corruption can be seen with GMEM passes using CP_BLIT especially when forced using `TU_DEBUG=gmem,unaligned_store`. Signed-off-by: Mark Collins Part-of: --- src/freedreno/vulkan/tu_clear_blit.cc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/freedreno/vulkan/tu_clear_blit.cc b/src/freedreno/vulkan/tu_clear_blit.cc index 9295a7f3a53..922dd2fd63d 100644 --- a/src/freedreno/vulkan/tu_clear_blit.cc +++ b/src/freedreno/vulkan/tu_clear_blit.cc @@ -3747,8 +3747,13 @@ store_cp_blit(struct tu_cmd_buffer *cmd, /* sync GMEM writes with CACHE. */ tu_emit_event_write(cmd, cs, FD_CACHE_INVALIDATE); + if (CHIP >= A7XX) + /* On A7XX, we need to wait for any CP_EVENT_WRITE::BLIT operations + * arising from GMEM load/clears to land before we can continue. + */ + tu_emit_event_write(cmd, cs, FD_CCU_FLUSH_BLIT_CACHE); - /* Wait for CACHE_INVALIDATE to land */ + /* Wait for cache event to land */ tu_cs_emit_wfi(cs); r2d_run(cmd, cs);