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anv: remove unnecessary Tile Cache flushes

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On Gfx12+, flushing tile cache ensures color/depth values are
globally visible, but that's expensive.  Most operations only
need values to be GT-visible which can be achieved with depth
or rt flush.  Remove a bunch of unnecessary Tile Cache flushes.
Fast clears and slow depth clears still require Tile Cache flush.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9834>
This commit is contained in:
Felix DeGrood 2021-03-16 21:02:35 -07:00 • committed by Marge Bot
parent a7bb74db7b
commit 6f26a51f47
3 changed files with 18 additions and 22 deletions
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3
src/intel/vulkan/anv_blorp.c
View file

@ -1657,6 +1657,7 @@ anv_image_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer,
*/
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
ANV_PIPE_TILE_CACHE_FLUSH_BIT |
ANV_PIPE_END_OF_PIPE_SYNC_BIT,
"after clear DS");
@ -1846,6 +1847,7 @@ anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
*/
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
ANV_PIPE_TILE_CACHE_FLUSH_BIT |
ANV_PIPE_END_OF_PIPE_SYNC_BIT,
"before fast clear mcs");
@ -1931,6 +1933,7 @@ anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer,
*/
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
ANV_PIPE_TILE_CACHE_FLUSH_BIT |
ANV_PIPE_END_OF_PIPE_SYNC_BIT,
"before fast clear ccs");

10
src/intel/vulkan/anv_private.h
View file

@ -2482,14 +2482,16 @@ anv_pipe_flush_bits_for_access_flags(struct anv_device *device,
* target. To make its content available to future operations, flush
* the render target cache.
*/
pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
ANV_PIPE_TILE_CACHE_FLUSH_BIT;
break;
case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
/* We're transitioning a buffer that was previously used as depth
* buffer. To make its content available to future operations, flush
* the depth cache.
*/
pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT |
ANV_PIPE_TILE_CACHE_FLUSH_BIT;
break;
case VK_ACCESS_TRANSFER_WRITE_BIT:
/* We're transitioning a buffer that was previously used as a
@ -2505,7 +2507,8 @@ anv_pipe_flush_bits_for_access_flags(struct anv_device *device,
* to future operations. And for depth related operations we also
* need to flush the depth cache.
*/
pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
ANV_PIPE_TILE_CACHE_FLUSH_BIT;
pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
break;
case VK_ACCESS_MEMORY_WRITE_BIT:
@ -2546,6 +2549,7 @@ anv_pipe_invalidate_bits_for_access_flags(struct anv_device *device,
* UBO from the buffer, so we need to invalidate constant cache.
*/
pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
pipe_bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT;
break;
case VK_ACCESS_INDEX_READ_BIT:
case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:

27
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -636,7 +636,8 @@ transition_depth_buffer(struct anv_cmd_buffer *cmd_buffer,
/* Getting into the pass-through state for Depth is tricky and involves
* both a resolve and an ambiguate. We don't handle that state right now
* as anv_layout_to_aux_state never returns it.
* as anv_layout_to_aux_state never returns it. Resolve/ambiguate will
* trigger depth clears which require tile cache flushes.
*/
assert(final_state != ISL_AUX_STATE_PASS_THROUGH);
@ -644,10 +645,16 @@ transition_depth_buffer(struct anv_cmd_buffer *cmd_buffer,
assert(initial_hiz_valid);
anv_image_hiz_op(cmd_buffer, image, VK_IMAGE_ASPECT_DEPTH_BIT,
0, base_layer, layer_count, ISL_AUX_OP_FULL_RESOLVE);
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_TILE_CACHE_FLUSH_BIT,
"after depth resolve");
} else if (final_needs_hiz && !initial_hiz_valid) {
assert(initial_depth_valid);
anv_image_hiz_op(cmd_buffer, image, VK_IMAGE_ASPECT_DEPTH_BIT,
0, base_layer, layer_count, ISL_AUX_OP_AMBIGUATE);
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_TILE_CACHE_FLUSH_BIT,
"after hiz resolve");
}
}
@ -2153,24 +2160,6 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
bits &= ~ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT;
}
if (GFX_VER >= 12 &&
((bits & ANV_PIPE_DEPTH_CACHE_FLUSH_BIT) ||
(bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT))) {
/* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush
* Enable):
*
* Unified Cache (Tile Cache Disabled):
*
* When the Color and Depth (Z) streams are enabled to be cached in
* the DC space of L2, Software must use "Render Target Cache Flush
* Enable" and "Depth Cache Flush Enable" along with "Tile Cache
* Flush" for getting the color and depth (Z) write data to be
* globally observable. In this mode of operation it is not required
* to set "CS Stall" upon setting "Tile Cache Flush" bit.
*/
bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT;
}
/* Wa_1409226450, Wait for EU to be idle before pipe control which
* invalidates the instruction cache
*/