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anv: Remove Tile Cache flush from SBA, Pipe Select

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Tile Cache flushing not required for State Base Address or
Pipe Select instructions.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9834>
This commit is contained in:
Felix DeGrood 2021-03-16 21:00:59 -07:00 • committed by Marge Bot
parent 1da9ff047e
commit a7bb74db7b
1 changed files with 0 additions and 8 deletions
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8
src/intel/vulkan/genX_cmd_buffer.c
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@ -99,9 +99,6 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
pc.DCFlushEnable = true;
pc.RenderTargetCacheFlushEnable = true;
pc.CommandStreamerStallEnable = true;
#if GFX_VER >= 12
pc.TileCacheFlushEnable = true;
#endif
#if GFX_VER == 12
/* Wa_1606662791:
*
@ -4996,8 +4993,6 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
pc.PostSyncOperation = NoWrite;
pc.CommandStreamerStallEnable = true;
#if GFX_VER >= 12
pc.TileCacheFlushEnable = true;
/* Wa_1409600907: "PIPE_CONTROL with Depth Stall Enable bit must be
* set with any PIPE_CONTROL with Depth Flush Enable bit set.
*/
@ -5012,9 +5007,6 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
pc.StateCacheInvalidationEnable = true;
pc.InstructionCacheInvalidateEnable = true;
pc.PostSyncOperation = NoWrite;
#if GFX_VER >= 12
pc.TileCacheFlushEnable = true;
#endif
anv_debug_dump_pc(pc);
}