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radv: Fix memory corruption loading RT pipeline cache entries.

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Fixes: ca2d96db51 ("radv: Add caching for RT pipelines.")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13789>
(cherry picked from commit 9494c566c2)
This commit is contained in:
Bas Nieuwenhuizen 2021-11-14 23:57:45 +01:00 • committed by Eric Engestrom
parent 503321ea7d
commit 6e1de95860
2 changed files with 2 additions and 1 deletions
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2
.pick_status.json
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@ -715,7 +715,7 @@
"description": "radv: Fix memory corruption loading RT pipeline cache entries.",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "ca2d96db51e5a47044ee02f8613bc463605c2bf8"
},

1
src/amd/vulkan/radv_pipeline_cache.c
View file

@ -109,6 +109,7 @@ entry_size(struct cache_entry *entry)
for (int i = 0; i < MESA_SHADER_STAGES; ++i)
if (entry->binary_sizes[i])
ret += entry->binary_sizes[i];
ret += sizeof(struct radv_pipeline_shader_stack_size) * entry->num_stack_sizes;
ret = align(ret, alignof(struct cache_entry));
return ret;
}