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i965/gen10: Implement WaForceRCPFEHangWorkaround

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This workaround doesn't fix any of the piglit hangs we've seen
on CNL. But it might be fixing something we haven't tested yet.

V2: Add the check for Post Sync Operation.
    Update the workaround comment.
    Use braces around if-else.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
This commit is contained in:
Anuj Phogat 2017-09-11 13:03:31 -07:00
parent 3cf4fe2219
commit d3d0fe4572
1 changed files with 23 additions and 0 deletions
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23
src/mesa/drivers/dri/i965/brw_pipe_control.c
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@ -89,6 +89,26 @@ gen7_cs_stall_every_four_pipe_controls(struct brw_context *brw, uint32_t flags)
return 0;
}
/* #1130 from gen10 workarounds page in h/w specs:
* "Enable Depth Stall on every Post Sync Op if Render target Cache Flush is
* not enabled in same PIPE CONTROL and Enable Pixel score board stall if
* Render target cache flush is enabled."
*
* Applicable to CNL B0 and C0 steppings only.
*/
static void
gen10_add_rcpfe_workaround_bits(uint32_t *flags)
{
if (*flags & PIPE_CONTROL_RENDER_TARGET_FLUSH) {
*flags = *flags | PIPE_CONTROL_STALL_AT_SCOREBOARD;
} else if (*flags &
(PIPE_CONTROL_WRITE_IMMEDIATE ||
PIPE_CONTROL_WRITE_DEPTH_COUNT ||
PIPE_CONTROL_WRITE_TIMESTAMP)) {
*flags = *flags | PIPE_CONTROL_DEPTH_STALL;
}
}
static void
brw_emit_pipe_control(struct brw_context *brw, uint32_t flags,
struct brw_bo *bo, uint32_t offset, uint64_t imm)
@ -109,6 +129,9 @@ brw_emit_pipe_control(struct brw_context *brw, uint32_t flags,
brw_emit_pipe_control_flush(brw, 0);
}
if (devinfo->gen == 10)
gen10_add_rcpfe_workaround_bits(&flags);
BEGIN_BATCH(6);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
OUT_BATCH(flags);