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iris: Fix AUX-TT invalidation

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In order to make sure RCS engine is idle, we need to add
DC flush + CS stall + Render target Cache flush + Depth Cache
on Gfx 12 and additional CCS cache flush on Gfx12.5.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23786>
This commit is contained in:
Sagar Ghuge 2023-06-20 22:05:08 -07:00
parent 26a7e997fb
commit 6be75d8aa2
1 changed files with 3 additions and 1 deletions
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4
src/gallium/drivers/iris/iris_state.c
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@ -5923,7 +5923,9 @@ genX(invalidate_aux_map_state)(struct iris_batch *batch)
iris_emit_end_of_pipe_sync(batch, "Invalidate aux map table",
PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_RENDER_TARGET_FLUSH |
PIPE_CONTROL_STATE_CACHE_INVALIDATE);
PIPE_CONTROL_STATE_CACHE_INVALIDATE |
(GFX_VERx10 == 125 ?
PIPE_CONTROL_CCS_CACHE_FLUSH : 0));
/* If the aux-map state number increased, then we need to rewrite the
* register. Rewriting the register is used to both set the aux-map