brw: Move AVG related validation

Couldn't find in the docs a reference for the types needing to match,
and simulator + MTL seem fine with mixing UD and UW, so not adding
a replacement for the removed assertions.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38877>
This commit is contained in:
Caio Oliveira 2025-12-02 11:50:34 -08:00 committed by Marge Bot
parent 6d8d733d4d
commit 6ae92d3372
2 changed files with 12 additions and 21 deletions

View file

@ -919,6 +919,7 @@ ALU2(SUBB)
ALU3(ADD3)
ALU1(MOV)
ALU2(MUL)
ALU2(AVG)
brw_eu_inst *
brw_ADD(struct brw_codegen *p, struct brw_reg dest,
@ -942,27 +943,6 @@ brw_ADD(struct brw_codegen *p, struct brw_reg dest,
return brw_alu2(p, BRW_OPCODE_ADD, dest, src0, src1);
}
brw_eu_inst *
brw_AVG(struct brw_codegen *p, struct brw_reg dest,
struct brw_reg src0, struct brw_reg src1)
{
assert(dest.type == src0.type);
assert(src0.type == src1.type);
switch (src0.type) {
case BRW_TYPE_B:
case BRW_TYPE_UB:
case BRW_TYPE_W:
case BRW_TYPE_UW:
case BRW_TYPE_D:
case BRW_TYPE_UD:
break;
default:
UNREACHABLE("Bad type for brw_AVG");
}
return brw_alu2(p, BRW_OPCODE_AVG, dest, src0, src1);
}
brw_eu_inst *
brw_LINE(struct brw_codegen *p, struct brw_reg dest,
struct brw_reg src0, struct brw_reg src1)

View file

@ -2258,6 +2258,17 @@ instruction_restrictions(const struct brw_isa_info *isa,
* instructions, the boundaries of a register should not be crossed.
*/
}
if (inst->opcode == BRW_OPCODE_AVG) {
ERROR_IF(!brw_type_is_int(inst->dst.type) ||
!brw_type_is_int(inst->src[0].type) ||
!brw_type_is_int(inst->src[1].type),
"AVG performs integer average. Float types not supported.");
ERROR_IF(brw_type_size_bytes(inst->dst.type) > 4 ||
brw_type_size_bytes(inst->src[0].type) > 4 ||
brw_type_size_bytes(inst->src[1].type) > 4,
"AVG does not support 64-bit types.");
}
}
static void