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brw: Move AVG related validation
Couldn't find in the docs a reference for the types needing to match, and simulator + MTL seem fine with mixing UD and UW, so not adding a replacement for the removed assertions. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38877>
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2 changed files with 12 additions and 21 deletions
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@ -919,6 +919,7 @@ ALU2(SUBB)
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ALU3(ADD3)
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ALU1(MOV)
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ALU2(MUL)
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ALU2(AVG)
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brw_eu_inst *
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brw_ADD(struct brw_codegen *p, struct brw_reg dest,
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@ -942,27 +943,6 @@ brw_ADD(struct brw_codegen *p, struct brw_reg dest,
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return brw_alu2(p, BRW_OPCODE_ADD, dest, src0, src1);
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}
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brw_eu_inst *
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brw_AVG(struct brw_codegen *p, struct brw_reg dest,
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struct brw_reg src0, struct brw_reg src1)
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{
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assert(dest.type == src0.type);
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assert(src0.type == src1.type);
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switch (src0.type) {
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case BRW_TYPE_B:
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case BRW_TYPE_UB:
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case BRW_TYPE_W:
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case BRW_TYPE_UW:
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case BRW_TYPE_D:
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case BRW_TYPE_UD:
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break;
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default:
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UNREACHABLE("Bad type for brw_AVG");
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}
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return brw_alu2(p, BRW_OPCODE_AVG, dest, src0, src1);
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}
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brw_eu_inst *
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brw_LINE(struct brw_codegen *p, struct brw_reg dest,
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struct brw_reg src0, struct brw_reg src1)
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@ -2258,6 +2258,17 @@ instruction_restrictions(const struct brw_isa_info *isa,
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* instructions, the boundaries of a register should not be crossed.
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*/
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}
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if (inst->opcode == BRW_OPCODE_AVG) {
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ERROR_IF(!brw_type_is_int(inst->dst.type) ||
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!brw_type_is_int(inst->src[0].type) ||
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!brw_type_is_int(inst->src[1].type),
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"AVG performs integer average. Float types not supported.");
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ERROR_IF(brw_type_size_bytes(inst->dst.type) > 4 ||
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brw_type_size_bytes(inst->src[0].type) > 4 ||
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brw_type_size_bytes(inst->src[1].type) > 4,
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"AVG does not support 64-bit types.");
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}
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}
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static void
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