diff --git a/src/intel/compiler/brw/brw_eu_emit.c b/src/intel/compiler/brw/brw_eu_emit.c index fe394c31706..27d70b793d8 100644 --- a/src/intel/compiler/brw/brw_eu_emit.c +++ b/src/intel/compiler/brw/brw_eu_emit.c @@ -919,6 +919,7 @@ ALU2(SUBB) ALU3(ADD3) ALU1(MOV) ALU2(MUL) +ALU2(AVG) brw_eu_inst * brw_ADD(struct brw_codegen *p, struct brw_reg dest, @@ -942,27 +943,6 @@ brw_ADD(struct brw_codegen *p, struct brw_reg dest, return brw_alu2(p, BRW_OPCODE_ADD, dest, src0, src1); } -brw_eu_inst * -brw_AVG(struct brw_codegen *p, struct brw_reg dest, - struct brw_reg src0, struct brw_reg src1) -{ - assert(dest.type == src0.type); - assert(src0.type == src1.type); - switch (src0.type) { - case BRW_TYPE_B: - case BRW_TYPE_UB: - case BRW_TYPE_W: - case BRW_TYPE_UW: - case BRW_TYPE_D: - case BRW_TYPE_UD: - break; - default: - UNREACHABLE("Bad type for brw_AVG"); - } - - return brw_alu2(p, BRW_OPCODE_AVG, dest, src0, src1); -} - brw_eu_inst * brw_LINE(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1) diff --git a/src/intel/compiler/brw/brw_eu_validate.c b/src/intel/compiler/brw/brw_eu_validate.c index 885b185a2b9..265c1dceea0 100644 --- a/src/intel/compiler/brw/brw_eu_validate.c +++ b/src/intel/compiler/brw/brw_eu_validate.c @@ -2258,6 +2258,17 @@ instruction_restrictions(const struct brw_isa_info *isa, * instructions, the boundaries of a register should not be crossed. */ } + + if (inst->opcode == BRW_OPCODE_AVG) { + ERROR_IF(!brw_type_is_int(inst->dst.type) || + !brw_type_is_int(inst->src[0].type) || + !brw_type_is_int(inst->src[1].type), + "AVG performs integer average. Float types not supported."); + ERROR_IF(brw_type_size_bytes(inst->dst.type) > 4 || + brw_type_size_bytes(inst->src[0].type) > 4 || + brw_type_size_bytes(inst->src[1].type) > 4, + "AVG does not support 64-bit types."); + } } static void