radv: ignore radv_disable_dcc{_mips} drirc options on GFX12

They shouldn't have any effects because on GFX12 DCC is transparent
to the userspace driver, and they should improve performance for the
games listed below:

- DOOM (2016)
- Wolfenstein II
- Red Dead Redemption 2
- WWE 2k23

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38481>

src/amd/vulkan/radv_device_memory.c

@@ -251,7 +251,7 @@ radv_alloc_memory(struct radv_device *device, const VkMemoryAllocateInfo *pAlloc
        * (see DCC tiling flags).
        */
       if (pdev->info.gfx_level >= GFX12 && pdev->info.gfx12_supports_dcc_write_compress_disable &&
-          domain == RADEON_DOMAIN_VRAM && (flags & RADEON_FLAG_NO_CPU_ACCESS) && !radv_is_dcc_disabled(instance)) {
+          domain == RADEON_DOMAIN_VRAM && (flags & RADEON_FLAG_NO_CPU_ACCESS) && !radv_is_dcc_disabled(pdev)) {
          flags |= RADEON_FLAG_GFX12_ALLOW_DCC;
       }
 

src/amd/vulkan/radv_formats.c

@@ -651,11 +651,10 @@ radv_get_modifier_flags(struct radv_physical_device *pdev, VkFormat format, uint
        * do not support DCC image stores or when explicitly disabled.
        */
       if (!ac_modifier_supports_dcc_image_stores(pdev->info.gfx_level, modifier) ||
-          radv_is_atomic_format_supported(format) ||
-          (instance->drirc.debug.disable_dcc_stores && pdev->info.gfx_level < GFX12))
+          radv_is_atomic_format_supported(format) || radv_are_dcc_stores_disabled(pdev))
          features &= ~VK_FORMAT_FEATURE_2_STORAGE_IMAGE_BIT;
 
-      if (radv_is_dcc_disabled(instance) || instance->debug_flags & RADV_DEBUG_NO_DISPLAY_DCC)
+      if (radv_is_dcc_disabled(pdev) || instance->debug_flags & RADV_DEBUG_NO_DISPLAY_DCC)
          return 0;
    }
 
@@ -1192,7 +1191,6 @@ radv_GetPhysicalDeviceImageFormatProperties2(VkPhysicalDevice physicalDevice,
                                              VkImageFormatProperties2 *base_props)
 {
    VK_FROM_HANDLE(radv_physical_device, pdev, physicalDevice);
-   const struct radv_instance *instance = radv_physical_device_instance(pdev);
    const VkPhysicalDeviceExternalImageFormatInfo *external_info = NULL;
    VkExternalImageFormatProperties *external_props = NULL;
    struct VkAndroidHardwareBufferUsageANDROID *android_usage = NULL;
@@ -1299,9 +1297,9 @@ radv_GetPhysicalDeviceImageFormatProperties2(VkPhysicalDevice physicalDevice,
          image_compression_props->imageCompressionFlags =
             pdev->use_hiz ? VK_IMAGE_COMPRESSION_DEFAULT_EXT : VK_IMAGE_COMPRESSION_DISABLED_EXT;
       } else {
-         image_compression_props->imageCompressionFlags =
-            (radv_is_dcc_disabled(instance) || pdev->info.gfx_level < GFX8) ? VK_IMAGE_COMPRESSION_DISABLED_EXT
-                                                                            : VK_IMAGE_COMPRESSION_DEFAULT_EXT;
+         image_compression_props->imageCompressionFlags = (radv_is_dcc_disabled(pdev) || pdev->info.gfx_level < GFX8)
+                                                             ? VK_IMAGE_COMPRESSION_DISABLED_EXT
+                                                             : VK_IMAGE_COMPRESSION_DEFAULT_EXT;
       }
    }
 
@@ -1312,7 +1310,7 @@ radv_GetPhysicalDeviceImageFormatProperties2(VkPhysicalDevice physicalDevice,
          might_enable_compression |= pdev->use_hiz && (base_info->usage & VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT);
       } else {
          might_enable_compression |=
-            !radv_is_dcc_disabled(instance) && (base_info->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT);
+            !radv_is_dcc_disabled(pdev) && (base_info->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT);
       }
 
       /**

src/amd/vulkan/radv_image.c

@@ -254,7 +254,7 @@ radv_use_dcc_for_image_early(struct radv_device *device, struct radv_image *imag
    const VkImageCompressionControlEXT *compression =
       vk_find_struct_const(pCreateInfo->pNext, IMAGE_COMPRESSION_CONTROL_EXT);
 
-   if (radv_is_dcc_disabled(instance) || (compression && compression->flags == VK_IMAGE_COMPRESSION_DISABLED_EXT)) {
+   if (radv_is_dcc_disabled(pdev) || (compression && compression->flags == VK_IMAGE_COMPRESSION_DISABLED_EXT)) {
       return false;
    }
 
@@ -298,12 +298,11 @@ radv_use_dcc_for_image_early(struct radv_device *device, struct radv_image *imag
    }
 
    /* Force disable DCC for mips to workaround game bugs. */
-   if (instance->drirc.debug.disable_dcc_mips && pCreateInfo->mipLevels > 1)
+   if (radv_are_dcc_mips_disabled(pdev) && pCreateInfo->mipLevels > 1)
       return false;
 
    /* Force disable DCC for stores to workaround game bugs. */
-   if (instance->drirc.debug.disable_dcc_stores && pdev->info.gfx_level < GFX12 &&
-       (pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT))
+   if (radv_are_dcc_stores_disabled(pdev) && (pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT))
       return false;
 
    /* DCC MSAA can't work on GFX10.3 and earlier without FMASK. */

src/amd/vulkan/radv_instance.c

@@ -313,12 +313,6 @@ radv_is_rt_wave64_enabled(const struct radv_instance *instance)
    return instance->perftest_flags & RADV_PERFTEST_RT_WAVE_64 || instance->drirc.debug.rt_wave64;
 }
 
-bool
-radv_is_dcc_disabled(const struct radv_instance *instance)
-{
-   return instance->debug_flags & RADV_DEBUG_NO_DCC || instance->drirc.debug.disable_dcc;
-}
-
 static const struct vk_instance_extension_table radv_instance_extensions_supported = {
    .KHR_device_group_creation = true,
    .KHR_external_fence_capabilities = true,

src/amd/vulkan/radv_instance.h

@@ -114,6 +114,4 @@ const char *radv_get_perftest_option_name(int id);
 
 bool radv_is_rt_wave64_enabled(const struct radv_instance *instance);
 
-bool radv_is_dcc_disabled(const struct radv_instance *instance);
-
 #endif /* RADV_INSTANCE_H */

src/amd/vulkan/radv_physical_device.c

@@ -211,6 +211,30 @@ radv_use_bvh8(const struct radv_physical_device *pdev)
    return pdev->info.gfx_level >= GFX12 && !radv_emulate_rt(pdev) && !(instance->debug_flags & RADV_DEBUG_BVH4);
 }
 
+bool
+radv_is_dcc_disabled(const struct radv_physical_device *pdev)
+{
+   const struct radv_instance *instance = radv_physical_device_instance(pdev);
+
+   return instance->debug_flags & RADV_DEBUG_NO_DCC ||
+          (instance->drirc.debug.disable_dcc && pdev->info.gfx_level < GFX12);
+}
+
+bool
+radv_are_dcc_stores_disabled(const struct radv_physical_device *pdev)
+{
+   const struct radv_instance *instance = radv_physical_device_instance(pdev);
+
+   return instance->drirc.debug.disable_dcc_stores && pdev->info.gfx_level < GFX12;
+}
+
+bool
+radv_are_dcc_mips_disabled(const struct radv_physical_device *pdev)
+{
+   const struct radv_instance *instance = radv_physical_device_instance(pdev);
+
+   return instance->drirc.debug.disable_dcc_mips && pdev->info.gfx_level < GFX12;
+}
 static void
 parse_hex(char *out, const char *in, unsigned length)
 {

src/amd/vulkan/radv_physical_device.h

@@ -297,6 +297,12 @@ bool radv_emulate_rt(const struct radv_physical_device *pdev);
 
 bool radv_use_bvh8(const struct radv_physical_device *pdev);
 
+bool radv_is_dcc_disabled(const struct radv_physical_device *pdev);
+
+bool radv_are_dcc_stores_disabled(const struct radv_physical_device *pdev);
+
+bool radv_are_dcc_mips_disabled(const struct radv_physical_device *pdev);
+
 uint32_t radv_find_memory_index(const struct radv_physical_device *pdev, VkMemoryPropertyFlags flags);
 
 VkResult create_null_physical_device(struct vk_instance *vk_instance);

src/util/driconf.h

@@ -720,11 +720,11 @@
 
 #define DRI_CONF_RADV_DISABLE_DCC(def) \
    DRI_CONF_OPT_B(radv_disable_dcc, def, \
-                  "Disable DCC for color images")
+                  "Disable DCC for color images on GFX8-GFX11.5")
 
 #define DRI_CONF_RADV_DISABLE_DCC_MIPS(def) \
    DRI_CONF_OPT_B(radv_disable_dcc_mips, def, \
-                  "Disable DCC for color images with mips")
+                  "Disable DCC for color images with mips on GFX8-GFX11.5")
 
 #define DRI_CONF_RADV_DISABLE_DCC_STORES(def) \
    DRI_CONF_OPT_B(radv_disable_dcc_stores, def, \