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isl/iris/anv: setup L1CacheControl based on surface and buffer usage

Browse source 
Patch chooses write through mode with storage surfaces when cache policy
is set via ISL_SURF_USAGE_CACHE_POLICY_WT.

This fixes rendering artifacts seen in:

   Space Engineers 2
   Hogwarts Legacy
   Plague Tale: Requiem

This was tested with some workloads on MTL and all on LNL/BMG. It fixes
Space Engineers 2 rendering artifacts but not the crash which is a
separate issue.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12714
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12750
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34044>
This commit is contained in:
Tapani Pälli 2025-03-05 14:45:18 +02:00 • committed by Marge Bot
parent 84510aea8f
commit 694f2bbeeb
8 changed files with 25 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/gallium/drivers/iris/driinfo_iris.h
View file

@ -15,6 +15,7 @@ DRI_CONF_SECTION_PERFORMANCE
DRI_CONFIG_INTEL_TBIMR(true)
DRI_CONFIG_INTEL_VF_DISTRIBUTION(true)
DRI_CONFIG_INTEL_TE_DISTRIBUTION(true)
DRI_CONFIG_INTEL_STORAGE_CACHE_POLICY_WT(false)
DRI_CONF_OPT_E(bo_reuse, 1, 0, 1, "Buffer object reuse",)
DRI_CONF_OPT_I(generated_indirect_threshold, 100, 0, INT32_MAX, "Generated indirect draw threshold")
DRI_CONF_SECTION_END

2
src/gallium/drivers/iris/iris_screen.c
View file

@ -747,6 +747,8 @@ iris_screen_create(int fd, const struct pipe_screen_config *config)
screen->isl_dev.sampler_route_to_lsc =
driQueryOptionb(config->options, "intel_sampler_route_to_lsc");
screen->isl_dev.l1_storage_wt =
driQueryOptionb(config->options, "intel_storage_cache_policy_wt");
iris_compiler_init(screen);

1
src/intel/isl/isl.h
View file

@ -1342,6 +1342,7 @@ struct isl_device {
/* Options to configure by the driver: */
bool sampler_route_to_lsc;
bool l1_storage_wt;
/**
* Write buffer length in the upper dword of the

12
src/intel/isl/isl_surface_state.c
View file

@ -488,8 +488,10 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
#endif
#if GFX_VERx10 >= 125
/* Setting L1 caching policy to Write-back mode. */
s.L1CacheControl = L1CC_WB;
/* Setting L1 caching policy to Write-back or Write-through mode. */
s.L1CacheControl =
(dev->l1_storage_wt && (info->view->usage & ISL_SURF_USAGE_STORAGE_BIT)) ?
L1CC_WT : L1CC_WB;
#endif
#if GFX_VER >= 6
@ -1095,8 +1097,10 @@ isl_genX(buffer_fill_state_s)(const struct isl_device *dev, void *state,
#endif
#if GFX_VERx10 >= 125
/* Setting L1 caching policy to Write-back mode. */
s.L1CacheControl = L1CC_WB;
/* Setting L1 caching policy to Write-back or Write-through mode. */
s.L1CacheControl =
(dev->l1_storage_wt && (info->usage & ISL_SURF_USAGE_STORAGE_BIT)) ?
L1CC_WT : L1CC_WB;
#endif
#if (GFX_VERx10 >= 75)

1
src/intel/vulkan/anv_instance.c
View file

@ -36,6 +36,7 @@ static const driOptionDescription anv_dri_options[] = {
DRI_CONFIG_INTEL_TBIMR(true)
DRI_CONFIG_INTEL_VF_DISTRIBUTION(true)
DRI_CONFIG_INTEL_TE_DISTRIBUTION(true)
DRI_CONFIG_INTEL_STORAGE_CACHE_POLICY_WT(false)
DRI_CONF_ANV_COMPRESSION_CONTROL_ENABLED(false)
DRI_CONF_ANV_FAKE_NONLOCAL_MEMORY(false)
DRI_CONF_OPT_E(intel_stack_id, 512, 256, 2048,

2
src/intel/vulkan/anv_physical_device.c
View file

@ -2649,6 +2649,8 @@ anv_physical_device_try_create(struct vk_instance *vk_instance,
device->isl_dev.buffer_length_in_aux_addr = !intel_needs_workaround(device->isl_dev.info, 14019708328);
device->isl_dev.sampler_route_to_lsc =
driQueryOptionb(&instance->dri_options, "intel_sampler_route_to_lsc");
device->isl_dev.l1_storage_wt =
driQueryOptionb(&instance->dri_options, "intel_storage_cache_policy_wt");
result = anv_physical_device_init_uuids(device);
if (result != VK_SUCCESS)

7
src/util/00-mesa-defaults.conf
View file

@ -924,6 +924,9 @@ TODO: document the other workarounds.
<application name="Aperture Desk Job" executable="deskjob">
<option name="anv_assume_full_subgroups" value="32" />
</application>
<application name="A Plague Tale : Requiem" executable="APlagueTaleRequiem_x64.exe">
<option name="intel_storage_cache_policy_wt" value="true" />
</application>
<application name="Breaking Limit" executable="GPUScoreVulkan">
<option name="anv_assume_full_subgroups_with_barrier" value="true" />
</application>
@ -995,6 +998,7 @@ TODO: document the other workarounds.
</application>
<application name="Hogwarts Legacy" executable="HogwartsLegacy.exe">
<option name="force_vk_vendor" value="-1" />
<option name="intel_storage_cache_policy_wt" value="true" />
</application>
<application name="DEATH STRANDING" executable="ds.exe">
<option name="force_vk_vendor" value="-1" />
@ -1011,6 +1015,9 @@ TODO: document the other workarounds.
<application name="Satisfactory EGS" executable="FactoryGameEGS-Win64-Shipping.exe">
<option name="force_vk_vendor" value="-1" />
</application>
<application name="Space Engineers 2" executable="SpaceEngineers2.exe">
<option name="intel_storage_cache_policy_wt" value="true" />
</application>
<application name="Dying Light 2" executable="DyingLightGame_x64_rwdi.exe">
<option name="force_vk_vendor" value="-1" />
</application>

3
src/util/driconf.h
View file

@ -336,6 +336,9 @@
#define DRI_CONFIG_INTEL_TE_DISTRIBUTION(def) \
DRI_CONF_OPT_B(intel_te_distribution, def, "Enable tesselation distribution")
#define DRI_CONFIG_INTEL_STORAGE_CACHE_POLICY_WT(def) \
DRI_CONF_OPT_B(intel_storage_cache_policy_wt, def, "Enable write-through cache policy for storage buffers/images.")
#define DRI_CONF_INTEL_ENABLE_WA_14018912822(def) \
DRI_CONF_OPT_B(intel_enable_wa_14018912822, def, \
"Intel workaround for using zero blend constants")