From 694f2bbeebba124afdff01b8ed288107ff163347 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tapani=20P=C3=A4lli?= Date: Wed, 5 Mar 2025 14:45:18 +0200 Subject: [PATCH] isl/iris/anv: setup L1CacheControl based on surface and buffer usage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Patch chooses write through mode with storage surfaces when cache policy is set via ISL_SURF_USAGE_CACHE_POLICY_WT. This fixes rendering artifacts seen in: Space Engineers 2 Hogwarts Legacy Plague Tale: Requiem This was tested with some workloads on MTL and all on LNL/BMG. It fixes Space Engineers 2 rendering artifacts but not the crash which is a separate issue. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12714 Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12750 Signed-off-by: Tapani Pälli Reviewed-by: Lionel Landwerlin Part-of: --- src/gallium/drivers/iris/driinfo_iris.h | 1 + src/gallium/drivers/iris/iris_screen.c | 2 ++ src/intel/isl/isl.h | 1 + src/intel/isl/isl_surface_state.c | 12 ++++++++---- src/intel/vulkan/anv_instance.c | 1 + src/intel/vulkan/anv_physical_device.c | 2 ++ src/util/00-mesa-defaults.conf | 7 +++++++ src/util/driconf.h | 3 +++ 8 files changed, 25 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/iris/driinfo_iris.h b/src/gallium/drivers/iris/driinfo_iris.h index 2e2ccff3d6a..b44ff4aa32e 100644 --- a/src/gallium/drivers/iris/driinfo_iris.h +++ b/src/gallium/drivers/iris/driinfo_iris.h @@ -15,6 +15,7 @@ DRI_CONF_SECTION_PERFORMANCE DRI_CONFIG_INTEL_TBIMR(true) DRI_CONFIG_INTEL_VF_DISTRIBUTION(true) DRI_CONFIG_INTEL_TE_DISTRIBUTION(true) + DRI_CONFIG_INTEL_STORAGE_CACHE_POLICY_WT(false) DRI_CONF_OPT_E(bo_reuse, 1, 0, 1, "Buffer object reuse",) DRI_CONF_OPT_I(generated_indirect_threshold, 100, 0, INT32_MAX, "Generated indirect draw threshold") DRI_CONF_SECTION_END diff --git a/src/gallium/drivers/iris/iris_screen.c b/src/gallium/drivers/iris/iris_screen.c index 2edfc8a7c50..6a40ba22a25 100644 --- a/src/gallium/drivers/iris/iris_screen.c +++ b/src/gallium/drivers/iris/iris_screen.c @@ -747,6 +747,8 @@ iris_screen_create(int fd, const struct pipe_screen_config *config) screen->isl_dev.sampler_route_to_lsc = driQueryOptionb(config->options, "intel_sampler_route_to_lsc"); + screen->isl_dev.l1_storage_wt = + driQueryOptionb(config->options, "intel_storage_cache_policy_wt"); iris_compiler_init(screen); diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index ed160d9e9bc..63c23e90d6f 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -1342,6 +1342,7 @@ struct isl_device { /* Options to configure by the driver: */ bool sampler_route_to_lsc; + bool l1_storage_wt; /** * Write buffer length in the upper dword of the diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index de9318758f7..b492a67edb0 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -488,8 +488,10 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, #endif #if GFX_VERx10 >= 125 - /* Setting L1 caching policy to Write-back mode. */ - s.L1CacheControl = L1CC_WB; + /* Setting L1 caching policy to Write-back or Write-through mode. */ + s.L1CacheControl = + (dev->l1_storage_wt && (info->view->usage & ISL_SURF_USAGE_STORAGE_BIT)) ? + L1CC_WT : L1CC_WB; #endif #if GFX_VER >= 6 @@ -1095,8 +1097,10 @@ isl_genX(buffer_fill_state_s)(const struct isl_device *dev, void *state, #endif #if GFX_VERx10 >= 125 - /* Setting L1 caching policy to Write-back mode. */ - s.L1CacheControl = L1CC_WB; + /* Setting L1 caching policy to Write-back or Write-through mode. */ + s.L1CacheControl = + (dev->l1_storage_wt && (info->usage & ISL_SURF_USAGE_STORAGE_BIT)) ? + L1CC_WT : L1CC_WB; #endif #if (GFX_VERx10 >= 75) diff --git a/src/intel/vulkan/anv_instance.c b/src/intel/vulkan/anv_instance.c index 6f5e2310004..416624b16ca 100644 --- a/src/intel/vulkan/anv_instance.c +++ b/src/intel/vulkan/anv_instance.c @@ -36,6 +36,7 @@ static const driOptionDescription anv_dri_options[] = { DRI_CONFIG_INTEL_TBIMR(true) DRI_CONFIG_INTEL_VF_DISTRIBUTION(true) DRI_CONFIG_INTEL_TE_DISTRIBUTION(true) + DRI_CONFIG_INTEL_STORAGE_CACHE_POLICY_WT(false) DRI_CONF_ANV_COMPRESSION_CONTROL_ENABLED(false) DRI_CONF_ANV_FAKE_NONLOCAL_MEMORY(false) DRI_CONF_OPT_E(intel_stack_id, 512, 256, 2048, diff --git a/src/intel/vulkan/anv_physical_device.c b/src/intel/vulkan/anv_physical_device.c index 816114665ff..a33798df1ee 100644 --- a/src/intel/vulkan/anv_physical_device.c +++ b/src/intel/vulkan/anv_physical_device.c @@ -2649,6 +2649,8 @@ anv_physical_device_try_create(struct vk_instance *vk_instance, device->isl_dev.buffer_length_in_aux_addr = !intel_needs_workaround(device->isl_dev.info, 14019708328); device->isl_dev.sampler_route_to_lsc = driQueryOptionb(&instance->dri_options, "intel_sampler_route_to_lsc"); + device->isl_dev.l1_storage_wt = + driQueryOptionb(&instance->dri_options, "intel_storage_cache_policy_wt"); result = anv_physical_device_init_uuids(device); if (result != VK_SUCCESS) diff --git a/src/util/00-mesa-defaults.conf b/src/util/00-mesa-defaults.conf index 5c89bb35ef8..71330785602 100644 --- a/src/util/00-mesa-defaults.conf +++ b/src/util/00-mesa-defaults.conf @@ -924,6 +924,9 @@ TODO: document the other workarounds. + + @@ -995,6 +998,7 @@ TODO: document the other workarounds.