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anv: program STATE_COMPUTE_MODE to flush the L1 cache

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This is required for upcoming resource barrier work to implement HDC
flush's.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
This commit is contained in:
Rohan Garg 2024-09-26 20:41:52 +02:00 • committed by Marge Bot
parent 47bc9da064
commit e55a7bc83a
1 changed files with 3 additions and 0 deletions
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3
src/intel/vulkan/genX_init_state.c
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@ -666,6 +666,7 @@ init_render_queue_state(struct anv_queue *queue, bool is_companion_rcs_batch)
cm.Mask1 = 0xffff;
#if GFX_VERx10 >= 200
cm.Mask2 = 0xffff;
cm.UAVCoherencyMode = FlushDataportL1;
#endif
}
anv_batch_emit(batch, GENX(3DSTATE_MESH_CONTROL), zero);
@ -808,6 +809,8 @@ init_compute_queue_state(struct anv_queue *queue)
cm.AsyncComputeThreadLimitMask = 0x7;
cm.ZPassAsyncComputeThreadLimitMask = 0x7;
cm.ZAsyncThrottlesettingsMask = 0x3;
cm.Mask2 = 0xffff;
cm.UAVCoherencyMode = FlushDataportL1;
#else
cm.PixelAsyncComputeThreadLimit = PACTL_Max24;
cm.ZPassAsyncComputeThreadLimit = ZPACTL_Max60;