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ac,radeonsi: remove gfx11 FW-based MCBP
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It's too slow to be usable. User queues could replace it.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38338>
This commit is contained in:
Marek Olšák 2025-11-09 12:25:12 -05:00 • committed by Marge Bot
parent f0aad5bd7e
commit 65837d8289
7 changed files with 11 additions and 83 deletions
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16
src/amd/common/ac_gpu_info.c
View file

@ -1477,12 +1477,6 @@ ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->fw_based_mcbp.shadow_alignment = fw_info.gfx.shadow_alignment;
info->fw_based_mcbp.csa_size = fw_info.gfx.csa_size;
info->fw_based_mcbp.csa_alignment = fw_info.gfx.csa_alignment;
} else if (info->gfx_level >= GFX11 && device_info.shadow_size > 0) {
info->has_fw_based_shadowing = true;
info->fw_based_mcbp.shadow_size = device_info.shadow_size;
info->fw_based_mcbp.shadow_alignment = device_info.shadow_alignment;
info->fw_based_mcbp.csa_size = device_info.csa_size;
info->fw_based_mcbp.csa_alignment = device_info.csa_alignment;
}
/* WARNING: Register shadowing decreases performance by up to 50% on GFX11 with current FW. */
@ -1858,16 +1852,6 @@ void ac_print_gpu_info(const struct radeon_info *info, FILE *f)
fprintf(f, " has_gang_submit = %u\n", info->has_gang_submit);
fprintf(f, " has_gpuvm_fault_query = %u\n", info->has_gpuvm_fault_query);
fprintf(f, " has_kernelq_reg_shadowing = %u\n", info->has_kernelq_reg_shadowing);
fprintf(f, " has_fw_based_shadowing = %u\n", info->has_fw_based_shadowing);
if (info->has_fw_based_shadowing) {
fprintf(f, " * shadow size: %u (alignment: %u)\n",
info->fw_based_mcbp.shadow_size,
info->fw_based_mcbp.shadow_alignment);
fprintf(f, " * csa size: %u (alignment: %u)\n",
info->fw_based_mcbp.csa_size,
info->fw_based_mcbp.csa_alignment);
}
fprintf(f, " has_default_zerovram_support = %u\n", info->has_default_zerovram_support);
fprintf(f, " has_tmz_support = %u\n", info->has_tmz_support);
fprintf(f, " has_trap_handler_support = %u\n", info->has_trap_handler_support);

1
src/amd/common/ac_gpu_info.h
View file

@ -339,7 +339,6 @@ struct radeon_info {
uint32_t csa_size;
uint32_t csa_alignment;
} fw_based_mcbp;
bool has_fw_based_shadowing;
/* Device supports hardware-accelerated raytracing using
* image_bvh*_intersect_ray instructions

6
src/amd/common/ac_shadowed_regs.c
View file

@ -3084,10 +3084,8 @@ struct ac_pm4_state *ac_create_shadowing_ib_preamble(const struct radeon_info *i
CC1_SHADOW_GLOBAL_UCONFIG(1) |
CC1_SHADOW_GLOBAL_CONFIG(1));
if (!info->has_fw_based_shadowing) {
for (unsigned i = 0; i < SI_NUM_REG_RANGES; i++)
ac_build_load_reg(info, pm4, i, gpu_address);
}
for (unsigned i = 0; i < SI_NUM_REG_RANGES; i++)
ac_build_load_reg(info, pm4, i, gpu_address);
ac_pm4_finalize(pm4);

41
src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c
View file

@ -19,38 +19,15 @@ bool si_init_cp_reg_shadowing(struct si_context *sctx)
si_pm4_free_state(sctx, sctx->cs_preamble_state, ~0);
sctx->cs_preamble_state = NULL;
} else if (sctx->uses_kernelq_reg_shadowing) {
if (sctx->screen->info.has_fw_based_shadowing) {
sctx->shadowing.registers =
si_aligned_buffer_create(sctx->b.screen,
PIPE_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
PIPE_USAGE_DEFAULT,
sctx->screen->info.fw_based_mcbp.shadow_size,
sctx->screen->info.fw_based_mcbp.shadow_alignment);
sctx->shadowing.csa =
si_aligned_buffer_create(sctx->b.screen,
PIPE_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
PIPE_USAGE_DEFAULT,
sctx->screen->info.fw_based_mcbp.csa_size,
sctx->screen->info.fw_based_mcbp.csa_alignment);
if (!sctx->shadowing.registers || !sctx->shadowing.csa) {
mesa_loge("cannot create register shadowing buffer(s)");
return false;
} else {
sctx->ws->cs_set_mcbp_reg_shadowing_va(&sctx->gfx_cs,
sctx->shadowing.registers->gpu_address,
sctx->shadowing.csa->gpu_address);
}
} else {
sctx->shadowing.registers =
si_aligned_buffer_create(sctx->b.screen,
PIPE_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
PIPE_USAGE_DEFAULT,
SI_SHADOWED_REG_BUFFER_SIZE,
4096);
if (!sctx->shadowing.registers) {
mesa_loge("cannot create a shadowed_regs buffer");
return false;
}
sctx->shadowing.registers =
si_aligned_buffer_create(sctx->b.screen,
PIPE_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
PIPE_USAGE_DEFAULT,
SI_SHADOWED_REG_BUFFER_SIZE,
4096);
if (!sctx->shadowing.registers) {
mesa_loge("cannot create a shadowed_regs buffer");
return false;
}
/* We need to clear the shadowed reg buffer. */

5
src/gallium/include/winsys/radeon_winsys.h
View file

@ -794,11 +794,6 @@ struct radeon_winsys {
*/
bool (*cs_set_pstate)(struct radeon_cmdbuf *rcs, enum radeon_ctx_pstate state);
/**
* Pass the VAs to the buffers where various information is saved by the FW during mcbp.
*/
void (*cs_set_mcbp_reg_shadowing_va)(struct radeon_cmdbuf *rcs, uint64_t regs_va,
uint64_t csa_va);
/**
* Submits the preamble IB, which is the IB that initializes immutable registers and states.
* This must be the first IB for that queue type, and it affects all current and future contexts.

23
src/gallium/winsys/amdgpu/drm/amdgpu_cs.cpp
View file

@ -1346,13 +1346,6 @@ static int amdgpu_cs_submit_ib_kernelq(struct amdgpu_cs *acs,
chunks[num_chunks].chunk_data = (uintptr_t)sem_chunk;
num_chunks++;
if (aws->info.has_fw_based_shadowing && acs->mcbp_fw_shadow_chunk.shadow_va) {
chunks[num_chunks].chunk_id = AMDGPU_CHUNK_ID_CP_GFX_SHADOW;
chunks[num_chunks].length_dw = sizeof(struct drm_amdgpu_cs_chunk_cp_gfx_shadow) / 4;
chunks[num_chunks].chunk_data = (uintptr_t)&acs->mcbp_fw_shadow_chunk;
num_chunks++;
}
/* Fence */
if (amdgpu_cs_has_user_fence(acs)) {
chunks[num_chunks].chunk_id = AMDGPU_CHUNK_ID_FENCE;
@ -2059,9 +2052,6 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index)
if (r || (unlikely(acs->noop) && acs->ip_type != AMD_IP_GFX))
amdgpu_fence_signalled(csc->fence);
if (unlikely(aws->info.has_fw_based_shadowing && acs->mcbp_fw_shadow_chunk.flags && r == 0))
acs->mcbp_fw_shadow_chunk.flags = 0;
csc->error_code = r;
/* Clear the buffer lists. */
@ -2281,16 +2271,6 @@ static bool amdgpu_bo_is_referenced(struct radeon_cmdbuf *rcs,
return amdgpu_bo_is_referenced_by_cs_with_usage(acs, bo, usage);
}
static void amdgpu_cs_set_mcbp_reg_shadowing_va(struct radeon_cmdbuf *rcs,uint64_t regs_va,
uint64_t csa_va)
{
struct amdgpu_cs *acs = amdgpu_cs(rcs);
acs->mcbp_fw_shadow_chunk.shadow_va = regs_va;
acs->mcbp_fw_shadow_chunk.csa_va = csa_va;
acs->mcbp_fw_shadow_chunk.gds_va = 0;
acs->mcbp_fw_shadow_chunk.flags = AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW;
}
static void amdgpu_winsys_fence_reference(struct radeon_winsys *rws,
struct pipe_fence_handle **dst,
struct pipe_fence_handle *src)
@ -2348,7 +2328,4 @@ void amdgpu_cs_init_functions(struct amdgpu_screen_winsys *sws)
sws->base.fence_import_sync_file = amdgpu_fence_import_sync_file;
sws->base.fence_export_sync_file = amdgpu_fence_export_sync_file;
sws->base.export_signalled_sync_file = amdgpu_export_signalled_sync_file;
if (sws->aws->info.has_fw_based_shadowing)
sws->base.cs_set_mcbp_reg_shadowing_va = amdgpu_cs_set_mcbp_reg_shadowing_va;
}

2
src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
View file

@ -153,8 +153,6 @@ struct amdgpu_cs {
struct util_queue_fence flush_completed;
struct pipe_fence_handle *next_fence;
struct pb_buffer_lean *preamble_ib_bo;
struct drm_amdgpu_cs_chunk_cp_gfx_shadow mcbp_fw_shadow_chunk;
};
struct amdgpu_fence {