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anv: Convert indirect to direct dispatch

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Saves unncessary PC and stall during encode phase.

Thanks to Felix for pointing out that CCS always needs a CS stall once
we add a pipe control, that will kill the performance for BVH
construction.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38513>
This commit is contained in:
Sagar Ghuge 2025-11-18 14:05:49 -08:00 • committed by Marge Bot
parent 15ffe6c524
commit f0aad5bd7e
1 changed files with 2 additions and 14 deletions
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16
src/intel/vulkan/genX_acceleration_structure.c
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@ -378,20 +378,8 @@ anv_encode_as(VkCommandBuffer commandBuffer, const struct vk_acceleration_struct
};
anv_bvh_build_set_args(commandBuffer, &args, sizeof(args));
/* L1/L2 caches flushes should have been dealt with by pipeline barriers.
* Unfortunately some platforms require L3 flush because CS (reading the
* ir_internal_node_count paramters from vk_ir_header) is not L3 coherent.
*/
if (!ANV_DEVINFO_HAS_COHERENT_L3_CS(cmd_buffer->device->info)) {
anv_add_pending_pipe_bits(cmd_buffer, ANV_PIPE_DATA_CACHE_FLUSH_BIT,
"ir internal node count for dispatch");
}
struct anv_address indirect_addr =
anv_address_from_u64(intermediate_header_addr +
offsetof(struct vk_ir_header, ir_internal_node_count));
anv_genX(cmd_buffer->device->info, cmd_buffer_dispatch_indirect)
(cmd_buffer, indirect_addr, true /* is_unaligned_size_x */);
anv_genX(cmd_buffer->device->info, cmd_dispatch_unaligned)
(commandBuffer, MAX2(state->leaf_node_count, 1), 1, 1);
}
static VkResult