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intel/clflush: Utilize clflushopt in intel_invalidate_range
On MTL ChromeOS boards, during AI based video conference, we were
observing a lot of overhead from invalidations. Upon debug, it was found
that we were using clflush in this function and that isn't efficient.
With this change, while executing compute workloads like zoo models, we
are getting ~25% performance improvements in a best case scenario.
Rework:
* Jordan: Call intel_clflushopt_range() rather than
__builtin_ia32_clflushopt() because intel_mem.c is not compiled
with -mclflushopt.
Backport-to: 24.1 24.2
Signed-off-by: Sushma Venkatesh Reddy <sushma.venkatesh.reddy@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30238>
(cherry picked from commit 2f6919e6c2)
This commit is contained in:
parent
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2 changed files with 11 additions and 2 deletions
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@ -214,7 +214,7 @@
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"description": "intel/clflush: Utilize clflushopt in intel_invalidate_range",
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"nominated": true,
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"nomination_type": 4,
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"resolution": 0,
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"resolution": 1,
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"main_sha": null,
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"because_sha": null,
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"notes": null
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@ -78,7 +78,7 @@ intel_invalidate_range(void *start, size_t size)
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if (size == 0)
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return;
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intel_clflush_range(start, size);
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intel_flush_range_no_fence(start, size);
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/* Modern Atom CPUs (Baytrail+) have issues with clflush serialization,
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* where mfence is not a sufficient synchronization barrier. We must
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@ -90,6 +90,15 @@ intel_invalidate_range(void *start, size_t size)
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* ("drm: Restore double clflush on the last partial cacheline")
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* and https://bugs.freedesktop.org/show_bug.cgi?id=92845.
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*/
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#ifdef HAVE___BUILTIN_IA32_CLFLUSHOPT
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/* clflushopt doesn't include an mfence like clflush */
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if (util_get_cpu_caps()->has_clflushopt) {
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__builtin_ia32_mfence();
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intel_clflushopt_range(start + size - 1, 1);
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__builtin_ia32_mfence();
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return;
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}
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#endif
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__builtin_ia32_clflush(start + size - 1);
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__builtin_ia32_mfence();
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}
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