diff --git a/.pick_status.json b/.pick_status.json
index 7be1dbb8143..0987b0f180f 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -214,7 +214,7 @@
         "description": "intel/clflush: Utilize clflushopt in intel_invalidate_range",
         "nominated": true,
         "nomination_type": 4,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null,
         "notes": null
diff --git a/src/intel/common/intel_mem.c b/src/intel/common/intel_mem.c
index c2e09a44371..6ebd48fd46c 100644
--- a/src/intel/common/intel_mem.c
+++ b/src/intel/common/intel_mem.c
@@ -78,7 +78,7 @@ intel_invalidate_range(void *start, size_t size)
    if (size == 0)
       return;
 
-   intel_clflush_range(start, size);
+   intel_flush_range_no_fence(start, size);
 
    /* Modern Atom CPUs (Baytrail+) have issues with clflush serialization,
     * where mfence is not a sufficient synchronization barrier.  We must
@@ -90,6 +90,15 @@ intel_invalidate_range(void *start, size_t size)
     * ("drm: Restore double clflush on the last partial cacheline")
     * and https://bugs.freedesktop.org/show_bug.cgi?id=92845.
     */
+#ifdef HAVE___BUILTIN_IA32_CLFLUSHOPT
+   /* clflushopt doesn't include an mfence like clflush */
+   if (util_get_cpu_caps()->has_clflushopt) {
+      __builtin_ia32_mfence();
+      intel_clflushopt_range(start + size - 1, 1);
+      __builtin_ia32_mfence();
+      return;
+   }
+#endif
    __builtin_ia32_clflush(start + size - 1);
    __builtin_ia32_mfence();
 }