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aco: Implement the new tessellation I/O related NIR intrinsics.

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Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9201>
This commit is contained in:
Timur Kristóf 2021-02-17 16:39:50 +01:00 • committed by Marge Bot
parent e10e74a7af
commit 5c95b32c6e
2 changed files with 32 additions and 0 deletions
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27
src/amd/compiler/aco_instruction_selection.cpp
View file

@ -8172,6 +8172,11 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
break;
}
case nir_intrinsic_load_local_invocation_index: {
if (ctx->stage.hw == HWStage::LS || ctx->stage.hw == HWStage::HS) {
bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), get_arg(ctx, ctx->args->ac.vs_rel_patch_id));
break;
}
Temp id = emit_mbcnt(ctx, bld.tmp(v1));
/* The tg_size bits [6:11] contain the subgroup id,
@ -8760,6 +8765,28 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
/* unused in the legacy pipeline, the HW keeps track of this for us */
break;
}
case nir_intrinsic_load_tess_rel_patch_id_amd: {
bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), get_tess_rel_patch_id(ctx));
break;
}
case nir_intrinsic_load_ring_tess_factors_amd: {
bld.smem(aco_opcode::s_load_dwordx4, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
ctx->program->private_segment_buffer, Operand(RING_HS_TESS_FACTOR * 16u));
break;
}
case nir_intrinsic_load_ring_tess_factors_offset_amd: {
bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), get_arg(ctx, ctx->args->ac.tcs_factor_offset));
break;
}
case nir_intrinsic_load_ring_tess_offchip_amd: {
bld.smem(aco_opcode::s_load_dwordx4, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
ctx->program->private_segment_buffer, Operand(RING_HS_TESS_OFFCHIP * 16u));
break;
}
case nir_intrinsic_load_ring_tess_offchip_offset_amd: {
bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), get_arg(ctx, ctx->args->ac.tess_offchip_offset));
break;
}
default:
isel_err(&instr->instr, "Unimplemented intrinsic instr");
abort();

5
src/amd/compiler/aco_instruction_selection_setup.cpp
View file

@ -778,6 +778,10 @@ void init_context(isel_context *ctx, nir_shader *shader)
case nir_intrinsic_read_invocation:
case nir_intrinsic_first_invocation:
case nir_intrinsic_ballot:
case nir_intrinsic_load_ring_tess_factors_amd:
case nir_intrinsic_load_ring_tess_factors_offset_amd:
case nir_intrinsic_load_ring_tess_offchip_amd:
case nir_intrinsic_load_ring_tess_offchip_offset_amd:
type = RegType::sgpr;
break;
case nir_intrinsic_load_sample_id:
@ -853,6 +857,7 @@ void init_context(isel_context *ctx, nir_shader *shader)
case nir_intrinsic_load_invocation_id:
case nir_intrinsic_load_primitive_id:
case nir_intrinsic_load_buffer_amd:
case nir_intrinsic_load_tess_rel_patch_id_amd:
type = RegType::vgpr;
break;
case nir_intrinsic_shuffle: