diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index 9b8df55388d..62664317dc9 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -8172,6 +8172,11 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
       break;
    }
    case nir_intrinsic_load_local_invocation_index: {
+      if (ctx->stage.hw == HWStage::LS || ctx->stage.hw == HWStage::HS) {
+         bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), get_arg(ctx, ctx->args->ac.vs_rel_patch_id));
+         break;
+      }
+
       Temp id = emit_mbcnt(ctx, bld.tmp(v1));
 
       /* The tg_size bits [6:11] contain the subgroup id,
@@ -8760,6 +8765,28 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
       /* unused in the legacy pipeline, the HW keeps track of this for us */
       break;
    }
+   case nir_intrinsic_load_tess_rel_patch_id_amd: {
+      bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), get_tess_rel_patch_id(ctx));
+      break;
+   }
+   case nir_intrinsic_load_ring_tess_factors_amd: {
+      bld.smem(aco_opcode::s_load_dwordx4, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
+               ctx->program->private_segment_buffer, Operand(RING_HS_TESS_FACTOR * 16u));
+      break;
+   }
+   case nir_intrinsic_load_ring_tess_factors_offset_amd: {
+      bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), get_arg(ctx, ctx->args->ac.tcs_factor_offset));
+      break;
+   }
+   case nir_intrinsic_load_ring_tess_offchip_amd: {
+      bld.smem(aco_opcode::s_load_dwordx4, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
+               ctx->program->private_segment_buffer, Operand(RING_HS_TESS_OFFCHIP * 16u));
+      break;
+   }
+   case nir_intrinsic_load_ring_tess_offchip_offset_amd: {
+      bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), get_arg(ctx, ctx->args->ac.tess_offchip_offset));
+      break;
+   }
    default:
       isel_err(&instr->instr, "Unimplemented intrinsic instr");
       abort();
diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp
index 3c34b4b0039..c7219150463 100644
--- a/src/amd/compiler/aco_instruction_selection_setup.cpp
+++ b/src/amd/compiler/aco_instruction_selection_setup.cpp
@@ -778,6 +778,10 @@ void init_context(isel_context *ctx, nir_shader *shader)
                   case nir_intrinsic_read_invocation:
                   case nir_intrinsic_first_invocation:
                   case nir_intrinsic_ballot:
+                  case nir_intrinsic_load_ring_tess_factors_amd:
+                  case nir_intrinsic_load_ring_tess_factors_offset_amd:
+                  case nir_intrinsic_load_ring_tess_offchip_amd:
+                  case nir_intrinsic_load_ring_tess_offchip_offset_amd:
                      type = RegType::sgpr;
                      break;
                   case nir_intrinsic_load_sample_id:
@@ -853,6 +857,7 @@ void init_context(isel_context *ctx, nir_shader *shader)
                   case nir_intrinsic_load_invocation_id:
                   case nir_intrinsic_load_primitive_id:
                   case nir_intrinsic_load_buffer_amd:
+                  case nir_intrinsic_load_tess_rel_patch_id_amd:
                      type = RegType::vgpr;
                      break;
                   case nir_intrinsic_shuffle: