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winsys/amdgpu: aws instead of ws for amdgpu_winsys

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Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27968>
This commit is contained in:
Yogesh Mohan Marimuthu 2024-03-04 10:05:44 +05:30 • committed by Marge Bot
parent c7e8486130
commit 5b6c0fdc97
6 changed files with 384 additions and 384 deletions
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344
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
View file

File diff suppressed because it is too large Load diff

30
src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
View file

@ -203,7 +203,7 @@ static struct amdgpu_bo_real_reusable_slab *get_real_bo_reusable_slab(struct amd
* to set the fence to NULL in the ring, which is why we return a pointer to a pointer.
*/
static inline struct pipe_fence_handle **
get_fence_from_ring(struct amdgpu_winsys *ws, struct amdgpu_seq_no_fences *fences,
get_fence_from_ring(struct amdgpu_winsys *aws, struct amdgpu_seq_no_fences *fences,
unsigned queue_index)
{
/* The caller should check if the BO has a fence. */
@ -211,12 +211,12 @@ get_fence_from_ring(struct amdgpu_winsys *ws, struct amdgpu_seq_no_fences *fence
assert(fences->valid_fence_mask & BITFIELD_BIT(queue_index));
uint_seq_no buffer_seq_no = fences->seq_no[queue_index];
uint_seq_no latest_seq_no = ws->queues[queue_index].latest_seq_no;
uint_seq_no latest_seq_no = aws->queues[queue_index].latest_seq_no;
bool fence_present = latest_seq_no - buffer_seq_no < AMDGPU_FENCE_RING_SIZE;
if (fence_present) {
struct pipe_fence_handle **fence =
&ws->queues[queue_index].fences[buffer_seq_no % AMDGPU_FENCE_RING_SIZE];
&aws->queues[queue_index].fences[buffer_seq_no % AMDGPU_FENCE_RING_SIZE];
if (*fence)
return fence;
@ -229,10 +229,10 @@ get_fence_from_ring(struct amdgpu_winsys *ws, struct amdgpu_seq_no_fences *fence
return NULL;
}
static inline uint_seq_no pick_latest_seq_no(struct amdgpu_winsys *ws, unsigned queue_index,
static inline uint_seq_no pick_latest_seq_no(struct amdgpu_winsys *aws, unsigned queue_index,
uint_seq_no n1, uint_seq_no n2)
{
uint_seq_no latest = ws->queues[queue_index].latest_seq_no;
uint_seq_no latest = aws->queues[queue_index].latest_seq_no;
/* Since sequence numbers can wrap around, we need to pick the later number that's logically
* before "latest". The trick is to subtract "latest + 1" to underflow integer such
@ -244,11 +244,11 @@ static inline uint_seq_no pick_latest_seq_no(struct amdgpu_winsys *ws, unsigned
return s1 >= s2 ? n1 : n2;
}
static inline void add_seq_no_to_list(struct amdgpu_winsys *ws, struct amdgpu_seq_no_fences *fences,
static inline void add_seq_no_to_list(struct amdgpu_winsys *aws, struct amdgpu_seq_no_fences *fences,
unsigned queue_index, uint_seq_no seq_no)
{
if (fences->valid_fence_mask & BITFIELD_BIT(queue_index)) {
fences->seq_no[queue_index] = pick_latest_seq_no(ws, queue_index, seq_no,
fences->seq_no[queue_index] = pick_latest_seq_no(aws, queue_index, seq_no,
fences->seq_no[queue_index]);
} else {
fences->seq_no[queue_index] = seq_no;
@ -256,13 +256,13 @@ static inline void add_seq_no_to_list(struct amdgpu_winsys *ws, struct amdgpu_se
}
}
bool amdgpu_bo_can_reclaim(struct amdgpu_winsys *ws, struct pb_buffer_lean *_buf);
struct pb_buffer_lean *amdgpu_bo_create(struct amdgpu_winsys *ws,
bool amdgpu_bo_can_reclaim(struct amdgpu_winsys *aws, struct pb_buffer_lean *_buf);
struct pb_buffer_lean *amdgpu_bo_create(struct amdgpu_winsys *aws,
uint64_t size,
unsigned alignment,
enum radeon_bo_domain domain,
enum radeon_bo_flag flags);
void amdgpu_bo_destroy(struct amdgpu_winsys *ws, struct pb_buffer_lean *_buf);
void amdgpu_bo_destroy(struct amdgpu_winsys *aws, struct pb_buffer_lean *_buf);
void *amdgpu_bo_map(struct radeon_winsys *rws,
struct pb_buffer_lean *buf,
struct radeon_cmdbuf *rcs,
@ -273,7 +273,7 @@ void amdgpu_bo_init_functions(struct amdgpu_screen_winsys *sws);
bool amdgpu_bo_can_reclaim_slab(void *priv, struct pb_slab_entry *entry);
struct pb_slab *amdgpu_bo_slab_alloc(void *priv, unsigned heap, unsigned entry_size,
unsigned group_index);
void amdgpu_bo_slab_free(struct amdgpu_winsys *ws, struct pb_slab *slab);
void amdgpu_bo_slab_free(struct amdgpu_winsys *aws, struct pb_slab *slab);
uint64_t amdgpu_bo_get_va(struct pb_buffer_lean *buf);
static inline struct amdgpu_winsys_bo *
@ -283,10 +283,10 @@ amdgpu_winsys_bo(struct pb_buffer_lean *bo)
}
static inline void
amdgpu_winsys_bo_reference(struct amdgpu_winsys *ws, struct amdgpu_winsys_bo **dst,
amdgpu_winsys_bo_reference(struct amdgpu_winsys *aws, struct amdgpu_winsys_bo **dst,
struct amdgpu_winsys_bo *src)
{
radeon_bo_reference(&ws->dummy_sws.base,
radeon_bo_reference(&aws->dummy_sws.base,
(struct pb_buffer_lean**)dst, (struct pb_buffer_lean*)src);
}
@ -299,9 +299,9 @@ amdgpu_winsys_bo_set_reference(struct amdgpu_winsys_bo **dst, struct amdgpu_wins
/* Unreference dst, but don't assign anything. */
static inline void
amdgpu_winsys_bo_drop_reference(struct amdgpu_winsys *ws, struct amdgpu_winsys_bo *dst)
amdgpu_winsys_bo_drop_reference(struct amdgpu_winsys *aws, struct amdgpu_winsys_bo *dst)
{
radeon_bo_drop_reference(&ws->dummy_sws.base, &dst->base);
radeon_bo_drop_reference(&aws->dummy_sws.base, &dst->base);
}
#ifdef __cplusplus

244
src/gallium/winsys/amdgpu/drm/amdgpu_cs.cpp
View file

@ -27,7 +27,7 @@
void amdgpu_fence_destroy(struct amdgpu_fence *fence)
{
amdgpu_cs_destroy_syncobj(fence->ws->dev, fence->syncobj);
amdgpu_cs_destroy_syncobj(fence->aws->dev, fence->syncobj);
if (fence->ctx)
amdgpu_ctx_reference(&fence->ctx, NULL);
@ -43,11 +43,11 @@ amdgpu_fence_create(struct amdgpu_cs *cs)
struct amdgpu_ctx *ctx = cs->ctx;
fence->reference.count = 1;
fence->ws = ctx->ws;
fence->aws = ctx->aws;
amdgpu_ctx_reference(&fence->ctx, ctx);
fence->ctx = ctx;
fence->ip_type = cs->ip_type;
if (amdgpu_cs_create_syncobj2(ctx->ws->dev, 0, &fence->syncobj)) {
if (amdgpu_cs_create_syncobj2(ctx->aws->dev, 0, &fence->syncobj)) {
free(fence);
return NULL;
}
@ -61,7 +61,7 @@ amdgpu_fence_create(struct amdgpu_cs *cs)
static struct pipe_fence_handle *
amdgpu_fence_import_syncobj(struct radeon_winsys *rws, int fd)
{
struct amdgpu_winsys *ws = amdgpu_winsys(rws);
struct amdgpu_winsys *aws = amdgpu_winsys(rws);
struct amdgpu_fence *fence = CALLOC_STRUCT(amdgpu_fence);
int r;
@ -69,10 +69,10 @@ amdgpu_fence_import_syncobj(struct radeon_winsys *rws, int fd)
return NULL;
pipe_reference_init(&fence->reference, 1);
fence->ws = ws;
fence->aws = aws;
fence->ip_type = 0xffffffff;
r = amdgpu_cs_import_syncobj(ws->dev, fd, &fence->syncobj);
r = amdgpu_cs_import_syncobj(aws->dev, fd, &fence->syncobj);
if (r) {
FREE(fence);
return NULL;
@ -87,26 +87,26 @@ amdgpu_fence_import_syncobj(struct radeon_winsys *rws, int fd)
static struct pipe_fence_handle *
amdgpu_fence_import_sync_file(struct radeon_winsys *rws, int fd)
{
struct amdgpu_winsys *ws = amdgpu_winsys(rws);
struct amdgpu_winsys *aws = amdgpu_winsys(rws);
struct amdgpu_fence *fence = CALLOC_STRUCT(amdgpu_fence);
if (!fence)
return NULL;
pipe_reference_init(&fence->reference, 1);
fence->ws = ws;
fence->aws = aws;
/* fence->ctx == NULL means that the fence is syncobj-based. */
/* Convert sync_file into syncobj. */
int r = amdgpu_cs_create_syncobj(ws->dev, &fence->syncobj);
int r = amdgpu_cs_create_syncobj(aws->dev, &fence->syncobj);
if (r) {
FREE(fence);
return NULL;
}
r = amdgpu_cs_syncobj_import_sync_file(ws->dev, fence->syncobj, fd);
r = amdgpu_cs_syncobj_import_sync_file(aws->dev, fence->syncobj, fd);
if (r) {
amdgpu_cs_destroy_syncobj(ws->dev, fence->syncobj);
amdgpu_cs_destroy_syncobj(aws->dev, fence->syncobj);
FREE(fence);
return NULL;
}
@ -120,35 +120,35 @@ amdgpu_fence_import_sync_file(struct radeon_winsys *rws, int fd)
static int amdgpu_fence_export_sync_file(struct radeon_winsys *rws,
struct pipe_fence_handle *pfence)
{
struct amdgpu_winsys *ws = amdgpu_winsys(rws);
struct amdgpu_winsys *aws = amdgpu_winsys(rws);
struct amdgpu_fence *fence = (struct amdgpu_fence*)pfence;
int fd, r;
util_queue_fence_wait(&fence->submitted);
/* Convert syncobj into sync_file. */
r = amdgpu_cs_syncobj_export_sync_file(ws->dev, fence->syncobj, &fd);
r = amdgpu_cs_syncobj_export_sync_file(aws->dev, fence->syncobj, &fd);
return r ? -1 : fd;
}
static int amdgpu_export_signalled_sync_file(struct radeon_winsys *rws)
{
struct amdgpu_winsys *ws = amdgpu_winsys(rws);
struct amdgpu_winsys *aws = amdgpu_winsys(rws);
uint32_t syncobj;
int fd = -1;
int r = amdgpu_cs_create_syncobj2(ws->dev, DRM_SYNCOBJ_CREATE_SIGNALED,
int r = amdgpu_cs_create_syncobj2(aws->dev, DRM_SYNCOBJ_CREATE_SIGNALED,
&syncobj);
if (r) {
return -1;
}
r = amdgpu_cs_syncobj_export_sync_file(ws->dev, syncobj, &fd);
r = amdgpu_cs_syncobj_export_sync_file(aws->dev, syncobj, &fd);
if (r) {
fd = -1;
}
amdgpu_cs_destroy_syncobj(ws->dev, syncobj);
amdgpu_cs_destroy_syncobj(aws->dev, syncobj);
return fd;
}
@ -207,7 +207,7 @@ bool amdgpu_fence_wait(struct pipe_fence_handle *fence, uint64_t timeout,
if ((uint64_t)abs_timeout == OS_TIMEOUT_INFINITE)
abs_timeout = INT64_MAX;
if (amdgpu_cs_syncobj_wait(afence->ws->dev, &afence->syncobj, 1,
if (amdgpu_cs_syncobj_wait(afence->aws->dev, &afence->syncobj, 1,
abs_timeout, 0, NULL))
return false;
@ -277,21 +277,21 @@ static struct radeon_winsys_ctx *amdgpu_ctx_create(struct radeon_winsys *rws,
if (!ctx)
return NULL;
ctx->ws = amdgpu_winsys(rws);
ctx->aws = amdgpu_winsys(rws);
ctx->reference.count = 1;
ctx->allow_context_lost = allow_context_lost;
r = amdgpu_cs_ctx_create2(ctx->ws->dev, amdgpu_priority, &ctx->ctx);
r = amdgpu_cs_ctx_create2(ctx->aws->dev, amdgpu_priority, &ctx->ctx);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_cs_ctx_create2 failed. (%i)\n", r);
goto error_create;
}
alloc_buffer.alloc_size = ctx->ws->info.gart_page_size;
alloc_buffer.phys_alignment = ctx->ws->info.gart_page_size;
alloc_buffer.alloc_size = ctx->aws->info.gart_page_size;
alloc_buffer.phys_alignment = ctx->aws->info.gart_page_size;
alloc_buffer.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
r = amdgpu_bo_alloc(ctx->ws->dev, &alloc_buffer, &buf_handle);
r = amdgpu_bo_alloc(ctx->aws->dev, &alloc_buffer, &buf_handle);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r);
goto error_user_fence_alloc;
@ -324,17 +324,17 @@ static void amdgpu_ctx_destroy(struct radeon_winsys_ctx *rwctx)
amdgpu_ctx_reference(&ctx, NULL);
}
static void amdgpu_pad_gfx_compute_ib(struct amdgpu_winsys *ws, enum amd_ip_type ip_type,
static void amdgpu_pad_gfx_compute_ib(struct amdgpu_winsys *aws, enum amd_ip_type ip_type,
uint32_t *ib, uint32_t *num_dw, unsigned leave_dw_space)
{
unsigned pad_dw_mask = ws->info.ip[ip_type].ib_pad_dw_mask;
unsigned pad_dw_mask = aws->info.ip[ip_type].ib_pad_dw_mask;
unsigned unaligned_dw = (*num_dw + leave_dw_space) & pad_dw_mask;
if (unaligned_dw) {
int remaining = pad_dw_mask + 1 - unaligned_dw;
/* Only pad by 1 dword with the type-2 NOP if necessary. */
if (remaining == 1 && ws->info.gfx_ib_pad_with_type2) {
if (remaining == 1 && aws->info.gfx_ib_pad_with_type2) {
ib[(*num_dw)++] = PKT2_NOP_PAD;
} else {
/* Pad with a single NOP packet to minimize CP overhead because NOP is a variable-sized
@ -369,24 +369,24 @@ static int amdgpu_submit_gfx_nop(struct amdgpu_ctx *ctx)
* that the reset is not complete.
*/
amdgpu_context_handle temp_ctx;
r = amdgpu_cs_ctx_create2(ctx->ws->dev, AMDGPU_CTX_PRIORITY_NORMAL, &temp_ctx);
r = amdgpu_cs_ctx_create2(ctx->aws->dev, AMDGPU_CTX_PRIORITY_NORMAL, &temp_ctx);
if (r)
return r;
request.preferred_heap = AMDGPU_GEM_DOMAIN_VRAM;
request.alloc_size = 4096;
request.phys_alignment = 4096;
r = amdgpu_bo_alloc(ctx->ws->dev, &request, &buf_handle);
r = amdgpu_bo_alloc(ctx->aws->dev, &request, &buf_handle);
if (r)
goto destroy_ctx;
r = amdgpu_va_range_alloc(ctx->ws->dev, amdgpu_gpu_va_range_general,
r = amdgpu_va_range_alloc(ctx->aws->dev, amdgpu_gpu_va_range_general,
request.alloc_size, request.phys_alignment,
0, &va, &va_handle,
AMDGPU_VA_RANGE_32_BIT | AMDGPU_VA_RANGE_HIGH);
if (r)
goto destroy_bo;
r = amdgpu_bo_va_op_raw(ctx->ws->dev, buf_handle, 0, request.alloc_size, va,
r = amdgpu_bo_va_op_raw(ctx->aws->dev, buf_handle, 0, request.alloc_size, va,
AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_PAGE_EXECUTABLE,
AMDGPU_VA_OP_MAP);
if (r)
@ -396,7 +396,7 @@ static int amdgpu_submit_gfx_nop(struct amdgpu_ctx *ctx)
if (r)
goto destroy_bo;
noop_dw_size = ctx->ws->info.ip[AMD_IP_GFX].ib_pad_dw_mask + 1;
noop_dw_size = ctx->aws->info.ip[AMD_IP_GFX].ib_pad_dw_mask + 1;
((uint32_t*)cpu)[0] = PKT3(PKT3_NOP, noop_dw_size - 2, 0);
amdgpu_bo_cpu_unmap(buf_handle);
@ -421,7 +421,7 @@ static int amdgpu_submit_gfx_nop(struct amdgpu_ctx *ctx)
chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
chunks[1].chunk_data = (uintptr_t)&ib_in;
r = amdgpu_cs_submit_raw2(ctx->ws->dev, temp_ctx, 0, 2, chunks, &seq_no);
r = amdgpu_cs_submit_raw2(ctx->aws->dev, temp_ctx, 0, 2, chunks, &seq_no);
destroy_bo:
if (va_handle)
@ -506,7 +506,7 @@ amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx *rwctx, bool full_reset_o
if (!(flags & AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS))
*reset_completed = true;
if (ctx->ws->info.drm_minor < 54 && ctx->ws->info.has_graphics)
if (ctx->aws->info.drm_minor < 54 && ctx->aws->info.has_graphics)
*reset_completed = amdgpu_submit_gfx_nop(ctx) == 0;
}
}
@ -657,7 +657,7 @@ static unsigned amdgpu_cs_add_buffer(struct radeon_cmdbuf *rcs,
return 0;
}
static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *ws,
static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *aws,
struct amdgpu_ib *main_ib,
struct amdgpu_cs *cs)
{
@ -701,20 +701,20 @@ static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *ws,
flags |= RADEON_FLAG_32BIT;
}
pb = amdgpu_bo_create(ws, buffer_size,
ws->info.gart_page_size,
pb = amdgpu_bo_create(aws, buffer_size,
aws->info.gart_page_size,
domain, (radeon_bo_flag)flags);
if (!pb)
return false;
mapped = (uint8_t*)amdgpu_bo_map(&ws->dummy_sws.base, pb, NULL, PIPE_MAP_WRITE);
mapped = (uint8_t*)amdgpu_bo_map(&aws->dummy_sws.base, pb, NULL, PIPE_MAP_WRITE);
if (!mapped) {
radeon_bo_reference(&ws->dummy_sws.base, &pb, NULL);
radeon_bo_reference(&aws->dummy_sws.base, &pb, NULL);
return false;
}
radeon_bo_reference(&ws->dummy_sws.base, &main_ib->big_buffer, pb);
radeon_bo_reference(&ws->dummy_sws.base, &pb, NULL);
radeon_bo_reference(&aws->dummy_sws.base, &main_ib->big_buffer, pb);
radeon_bo_reference(&aws->dummy_sws.base, &pb, NULL);
main_ib->gpu_address = amdgpu_bo_get_va(main_ib->big_buffer);
main_ib->big_buffer_cpu_ptr = mapped;
@ -723,7 +723,7 @@ static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *ws,
return true;
}
static bool amdgpu_get_new_ib(struct amdgpu_winsys *ws,
static bool amdgpu_get_new_ib(struct amdgpu_winsys *aws,
struct radeon_cmdbuf *rcs,
struct amdgpu_ib *main_ib,
struct amdgpu_cs *cs)
@ -755,7 +755,7 @@ static bool amdgpu_get_new_ib(struct amdgpu_winsys *ws,
/* Allocate a new buffer for IBs if the current buffer is all used. */
if (!main_ib->big_buffer ||
main_ib->used_ib_space + ib_size > main_ib->big_buffer->size) {
if (!amdgpu_ib_new_buffer(ws, main_ib, cs))
if (!amdgpu_ib_new_buffer(aws, main_ib, cs))
return false;
}
@ -790,16 +790,16 @@ static void amdgpu_set_ib_size(struct radeon_cmdbuf *rcs, struct amdgpu_ib *ib)
}
}
static void amdgpu_ib_finalize(struct amdgpu_winsys *ws, struct radeon_cmdbuf *rcs,
static void amdgpu_ib_finalize(struct amdgpu_winsys *aws, struct radeon_cmdbuf *rcs,
struct amdgpu_ib *ib, enum amd_ip_type ip_type)
{
amdgpu_set_ib_size(rcs, ib);
ib->used_ib_space += rcs->current.cdw * 4;
ib->used_ib_space = align(ib->used_ib_space, ws->info.ip[ip_type].ib_alignment);
ib->used_ib_space = align(ib->used_ib_space, aws->info.ip[ip_type].ib_alignment);
ib->max_ib_bytes = MAX2(ib->max_ib_bytes, (rcs->prev_dw + rcs->current.cdw) * 4);
}
static bool amdgpu_init_cs_context(struct amdgpu_winsys *ws,
static bool amdgpu_init_cs_context(struct amdgpu_winsys *aws,
struct amdgpu_cs_context *cs,
enum amd_ip_type ip_type)
{
@ -831,20 +831,20 @@ static void cleanup_fence_list(struct amdgpu_fence_list *fences)
fences->num = 0;
}
static void amdgpu_cs_context_cleanup_buffers(struct amdgpu_winsys *ws, struct amdgpu_cs_context *cs)
static void amdgpu_cs_context_cleanup_buffers(struct amdgpu_winsys *aws, struct amdgpu_cs_context *cs)
{
for (unsigned i = 0; i < ARRAY_SIZE(cs->buffer_lists); i++) {
struct amdgpu_cs_buffer *buffers = cs->buffer_lists[i].buffers;
unsigned num_buffers = cs->buffer_lists[i].num_buffers;
for (unsigned j = 0; j < num_buffers; j++)
amdgpu_winsys_bo_drop_reference(ws, buffers[j].bo);
amdgpu_winsys_bo_drop_reference(aws, buffers[j].bo);
cs->buffer_lists[i].num_buffers = 0;
}
}
static void amdgpu_cs_context_cleanup(struct amdgpu_winsys *ws, struct amdgpu_cs_context *cs)
static void amdgpu_cs_context_cleanup(struct amdgpu_winsys *aws, struct amdgpu_cs_context *cs)
{
cs->seq_no_dependencies.valid_fence_mask = 0;
cleanup_fence_list(&cs->syncobj_dependencies);
@ -853,10 +853,10 @@ static void amdgpu_cs_context_cleanup(struct amdgpu_winsys *ws, struct amdgpu_cs
cs->last_added_bo = NULL;
}
static void amdgpu_destroy_cs_context(struct amdgpu_winsys *ws, struct amdgpu_cs_context *cs)
static void amdgpu_destroy_cs_context(struct amdgpu_winsys *aws, struct amdgpu_cs_context *cs)
{
amdgpu_cs_context_cleanup_buffers(ws, cs);
amdgpu_cs_context_cleanup(ws, cs);
amdgpu_cs_context_cleanup_buffers(aws, cs);
amdgpu_cs_context_cleanup(aws, cs);
for (unsigned i = 0; i < ARRAY_SIZE(cs->buffer_lists); i++)
FREE(cs->buffer_lists[i].buffers);
FREE(cs->syncobj_dependencies.list);
@ -896,18 +896,18 @@ amdgpu_cs_create(struct radeon_cmdbuf *rcs,
util_queue_fence_init(&cs->flush_completed);
cs->ws = ctx->ws;
cs->aws = ctx->aws;
cs->ctx = ctx;
cs->flush_cs = flush;
cs->flush_data = flush_ctx;
cs->ip_type = ip_type;
cs->noop = ctx->ws->noop_cs;
cs->has_chaining = ctx->ws->info.gfx_level >= GFX7 &&
cs->noop = ctx->aws->noop_cs;
cs->has_chaining = ctx->aws->info.gfx_level >= GFX7 &&
(ip_type == AMD_IP_GFX || ip_type == AMD_IP_COMPUTE);
/* Compute the queue index by counting the IPs that have queues. */
assert(ip_type < ARRAY_SIZE(ctx->ws->info.ip));
assert(ctx->ws->info.ip[ip_type].num_queues);
assert(ip_type < ARRAY_SIZE(ctx->aws->info.ip));
assert(ctx->aws->info.ip[ip_type].num_queues);
if (ip_uses_alt_fence(ip_type)) {
cs->queue_index = INT_MAX;
@ -915,8 +915,8 @@ amdgpu_cs_create(struct radeon_cmdbuf *rcs,
} else {
cs->queue_index = 0;
for (unsigned i = 0; i < ARRAY_SIZE(ctx->ws->info.ip); i++) {
if (!ctx->ws->info.ip[i].num_queues || ip_uses_alt_fence((amd_ip_type)i))
for (unsigned i = 0; i < ARRAY_SIZE(ctx->aws->info.ip); i++) {
if (!ctx->aws->info.ip[i].num_queues || ip_uses_alt_fence((amd_ip_type)i))
continue;
if (i == ip_type)
@ -933,13 +933,13 @@ amdgpu_cs_create(struct radeon_cmdbuf *rcs,
amdgpu_cs_chunk_fence_info_to_data(&fence_info,
(struct drm_amdgpu_cs_chunk_data*)&cs->fence_chunk);
if (!amdgpu_init_cs_context(ctx->ws, &cs->csc1, ip_type)) {
if (!amdgpu_init_cs_context(ctx->aws, &cs->csc1, ip_type)) {
FREE(cs);
return false;
}
if (!amdgpu_init_cs_context(ctx->ws, &cs->csc2, ip_type)) {
amdgpu_destroy_cs_context(ctx->ws, &cs->csc1);
if (!amdgpu_init_cs_context(ctx->aws, &cs->csc2, ip_type)) {
amdgpu_destroy_cs_context(ctx->aws, &cs->csc1);
FREE(cs);
return false;
}
@ -954,20 +954,20 @@ amdgpu_cs_create(struct radeon_cmdbuf *rcs,
cs->csc1.buffer_indices_hashlist = cs->buffer_indices_hashlist;
cs->csc2.buffer_indices_hashlist = cs->buffer_indices_hashlist;
cs->csc1.ws = ctx->ws;
cs->csc2.ws = ctx->ws;
cs->csc1.aws = ctx->aws;
cs->csc2.aws = ctx->aws;
rcs->priv = cs;
if (!amdgpu_get_new_ib(ctx->ws, rcs, &cs->main_ib, cs)) {
amdgpu_destroy_cs_context(ctx->ws, &cs->csc2);
amdgpu_destroy_cs_context(ctx->ws, &cs->csc1);
if (!amdgpu_get_new_ib(ctx->aws, rcs, &cs->main_ib, cs)) {
amdgpu_destroy_cs_context(ctx->aws, &cs->csc2);
amdgpu_destroy_cs_context(ctx->aws, &cs->csc1);
FREE(cs);
rcs->priv = NULL;
return false;
}
p_atomic_inc(&ctx->ws->num_cs);
p_atomic_inc(&ctx->aws->num_cs);
return true;
}
@ -976,14 +976,14 @@ amdgpu_cs_setup_preemption(struct radeon_cmdbuf *rcs, const uint32_t *preamble_i
unsigned preamble_num_dw)
{
struct amdgpu_cs *cs = amdgpu_cs(rcs);
struct amdgpu_winsys *ws = cs->ws;
struct amdgpu_winsys *aws = cs->aws;
struct amdgpu_cs_context *csc[2] = {&cs->csc1, &cs->csc2};
unsigned size = align(preamble_num_dw * 4, ws->info.ip[AMD_IP_GFX].ib_alignment);
unsigned size = align(preamble_num_dw * 4, aws->info.ip[AMD_IP_GFX].ib_alignment);
struct pb_buffer_lean *preamble_bo;
uint32_t *map;
/* Create the preamble IB buffer. */
preamble_bo = amdgpu_bo_create(ws, size, ws->info.ip[AMD_IP_GFX].ib_alignment,
preamble_bo = amdgpu_bo_create(aws, size, aws->info.ip[AMD_IP_GFX].ib_alignment,
RADEON_DOMAIN_VRAM,
(radeon_bo_flag)
(RADEON_FLAG_NO_INTERPROCESS_SHARING |
@ -992,10 +992,10 @@ amdgpu_cs_setup_preemption(struct radeon_cmdbuf *rcs, const uint32_t *preamble_i
if (!preamble_bo)
return false;
map = (uint32_t*)amdgpu_bo_map(&ws->dummy_sws.base, preamble_bo, NULL,
map = (uint32_t*)amdgpu_bo_map(&aws->dummy_sws.base, preamble_bo, NULL,
(pipe_map_flags)(PIPE_MAP_WRITE | RADEON_MAP_TEMPORARY));
if (!map) {
radeon_bo_reference(&ws->dummy_sws.base, &preamble_bo, NULL);
radeon_bo_reference(&aws->dummy_sws.base, &preamble_bo, NULL);
return false;
}
@ -1003,8 +1003,8 @@ amdgpu_cs_setup_preemption(struct radeon_cmdbuf *rcs, const uint32_t *preamble_i
memcpy(map, preamble_ib, preamble_num_dw * 4);
/* Pad the IB. */
amdgpu_pad_gfx_compute_ib(ws, cs->ip_type, map, &preamble_num_dw, 0);
amdgpu_bo_unmap(&ws->dummy_sws.base, preamble_bo);
amdgpu_pad_gfx_compute_ib(aws, cs->ip_type, map, &preamble_num_dw, 0);
amdgpu_bo_unmap(&aws->dummy_sws.base, preamble_bo);
for (unsigned i = 0; i < 2; i++) {
csc[i]->chunk_ib[IB_PREAMBLE].va_start = amdgpu_bo_get_va(preamble_bo);
@ -1066,7 +1066,7 @@ static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw)
rcs->max_prev = new_max_prev;
}
if (!amdgpu_ib_new_buffer(cs->ws, main_ib, cs))
if (!amdgpu_ib_new_buffer(cs->aws, main_ib, cs))
return false;
assert(main_ib->used_ib_space == 0);
@ -1076,14 +1076,14 @@ static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw)
rcs->current.max_dw += cs_epilog_dw;
/* Pad with NOPs but leave 4 dwords for INDIRECT_BUFFER. */
amdgpu_pad_gfx_compute_ib(cs->ws, cs->ip_type, rcs->current.buf, &rcs->current.cdw, 4);
amdgpu_pad_gfx_compute_ib(cs->aws, cs->ip_type, rcs->current.buf, &rcs->current.cdw, 4);
radeon_emit(rcs, PKT3(PKT3_INDIRECT_BUFFER, 2, 0));
radeon_emit(rcs, va);
radeon_emit(rcs, va >> 32);
uint32_t *new_ptr_ib_size = &rcs->current.buf[rcs->current.cdw++];
assert((rcs->current.cdw & cs->ws->info.ip[cs->ip_type].ib_pad_dw_mask) == 0);
assert((rcs->current.cdw & cs->aws->info.ip[cs->ip_type].ib_pad_dw_mask) == 0);
assert(rcs->current.cdw <= rcs->current.max_dw);
amdgpu_set_ib_size(rcs, main_ib);
@ -1180,7 +1180,7 @@ static void amdgpu_cs_add_fence_dependency(struct radeon_cmdbuf *rcs,
if (!fence->imported) {
/* Ignore idle fences. This will only check the user fence in memory. */
if (!amdgpu_fence_wait((struct pipe_fence_handle *)fence, 0, false)) {
add_seq_no_to_list(acs->ws, &cs->seq_no_dependencies, fence->queue_index,
add_seq_no_to_list(acs->aws, &cs->seq_no_dependencies, fence->queue_index,
fence->queue_seq_no);
}
}
@ -1237,7 +1237,7 @@ template<bool QUEUE_USES_ALT_FENCE>
static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index)
{
struct amdgpu_cs *acs = (struct amdgpu_cs*)job;
struct amdgpu_winsys *ws = acs->ws;
struct amdgpu_winsys *aws = acs->aws;
struct amdgpu_cs_context *cs = acs->cst;
int r;
uint64_t seq_no = 0;
@ -1245,14 +1245,14 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index)
assert(QUEUE_USES_ALT_FENCE == acs->uses_alt_fence);
simple_mtx_lock(&ws->bo_fence_lock);
simple_mtx_lock(&aws->bo_fence_lock);
unsigned queue_index;
struct amdgpu_queue *queue;
uint_seq_no prev_seq_no, next_seq_no;
if (!QUEUE_USES_ALT_FENCE) {
queue_index = acs->queue_index;
queue = &ws->queues[queue_index];
queue = &aws->queues[queue_index];
prev_seq_no = queue->latest_seq_no;
/* Generate a per queue sequence number. The logic is similar to the kernel side amdgpu seqno,
@ -1276,10 +1276,10 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index)
amdgpu_fence_reference(&tmp_fence, *oldest_fence);
/* Unlock the mutex before waiting. */
simple_mtx_unlock(&ws->bo_fence_lock);
simple_mtx_unlock(&aws->bo_fence_lock);
amdgpu_fence_wait(tmp_fence, OS_TIMEOUT_INFINITE, false);
amdgpu_fence_reference(&tmp_fence, NULL);
simple_mtx_lock(&ws->bo_fence_lock);
simple_mtx_lock(&aws->bo_fence_lock);
}
/* Remove the idle fence from the ring. */
@ -1303,8 +1303,8 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index)
struct amdgpu_fence *prev_fence =
(struct amdgpu_fence*)queue->fences[prev_seq_no % AMDGPU_FENCE_RING_SIZE];
if (prev_fence && (ws->info.ip[acs->ip_type].num_queues > 1 || queue->last_ctx != acs->ctx))
add_seq_no_to_list(ws, &seq_no_dependencies, queue_index, prev_seq_no);
if (prev_fence && (aws->info.ip[acs->ip_type].num_queues > 1 || queue->last_ctx != acs->ctx))
add_seq_no_to_list(aws, &seq_no_dependencies, queue_index, prev_seq_no);
}
/* Since the kernel driver doesn't synchronize execution between different
@ -1322,7 +1322,7 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index)
struct amdgpu_cs_buffer *buffer = &slab_entry_buffers[i];
struct amdgpu_winsys_bo *bo = buffer->bo;
amdgpu_add_fences_to_dependencies(ws, cs, queue_index_bit, &seq_no_dependencies, bo,
amdgpu_add_fences_to_dependencies(aws, cs, queue_index_bit, &seq_no_dependencies, bo,
buffer->usage);
if (QUEUE_USES_ALT_FENCE)
amdgpu_fence_reference(&bo->alt_fence, cs->fence);
@ -1350,7 +1350,7 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index)
struct amdgpu_cs_buffer *buffer = &sparse_buffers[i];
struct amdgpu_winsys_bo *bo = buffer->bo;
amdgpu_add_fences_to_dependencies(ws, cs, queue_index_bit, &seq_no_dependencies, bo,
amdgpu_add_fences_to_dependencies(aws, cs, queue_index_bit, &seq_no_dependencies, bo,
buffer->usage);
if (QUEUE_USES_ALT_FENCE)
amdgpu_fence_reference(&bo->alt_fence, cs->fence);
@ -1395,7 +1395,7 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index)
struct amdgpu_cs_buffer *buffer = &real_buffers[i];
struct amdgpu_winsys_bo *bo = buffer->bo;
amdgpu_add_fences_to_dependencies(ws, cs, queue_index_bit, &seq_no_dependencies, bo,
amdgpu_add_fences_to_dependencies(aws, cs, queue_index_bit, &seq_no_dependencies, bo,
buffer->usage);
if (QUEUE_USES_ALT_FENCE)
amdgpu_fence_reference(&bo->alt_fence, cs->fence);
@ -1442,7 +1442,7 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index)
bool valid = seq_no_dependencies.valid_fence_mask & BITFIELD_BIT(i);
uint_seq_no old = seq_no_dependencies.seq_no[i];
add_seq_no_to_list(ws, &seq_no_dependencies, i, ws->queues[i].latest_seq_no);
add_seq_no_to_list(aws, &seq_no_dependencies, i, aws->queues[i].latest_seq_no);
uint_seq_no new = seq_no_dependencies.seq_no[i];
if (!valid)
@ -1456,7 +1456,7 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index)
/* Convert the sequence numbers we gathered to fence dependencies. */
u_foreach_bit(i, seq_no_dependencies.valid_fence_mask) {
struct pipe_fence_handle **fence = get_fence_from_ring(ws, &seq_no_dependencies, i);
struct pipe_fence_handle **fence = get_fence_from_ring(aws, &seq_no_dependencies, i);
if (fence) {
/* If it's idle, don't add it to the list of dependencies. */
@ -1476,30 +1476,30 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index)
/* Update the last used context in the queue. */
amdgpu_ctx_reference(&queue->last_ctx, acs->ctx);
}
simple_mtx_unlock(&ws->bo_fence_lock);
simple_mtx_unlock(&aws->bo_fence_lock);
#ifdef DEBUG
/* Prepare the buffer list. */
if (ws->debug_all_bos) {
if (aws->debug_all_bos) {
/* The buffer list contains all buffers. This is a slow path that
* ensures that no buffer is missing in the BO list.
*/
simple_mtx_lock(&ws->global_bo_list_lock);
simple_mtx_lock(&aws->global_bo_list_lock);
bo_list = (struct drm_amdgpu_bo_list_entry *)
alloca(ws->num_buffers * sizeof(struct drm_amdgpu_bo_list_entry));
alloca(aws->num_buffers * sizeof(struct drm_amdgpu_bo_list_entry));
num_real_buffers = 0;
list_for_each_entry(struct amdgpu_bo_real, bo, &ws->global_bo_list, global_list_item) {
list_for_each_entry(struct amdgpu_bo_real, bo, &aws->global_bo_list, global_list_item) {
bo_list[num_real_buffers].bo_handle = bo->kms_handle;
bo_list[num_real_buffers].bo_priority = 0;
++num_real_buffers;
}
simple_mtx_unlock(&ws->global_bo_list_lock);
simple_mtx_unlock(&aws->global_bo_list_lock);
}
#endif
if (acs->ip_type == AMD_IP_GFX)
ws->gfx_bo_list_counter += num_real_buffers;
aws->gfx_bo_list_counter += num_real_buffers;
struct drm_amdgpu_cs_chunk chunks[8];
unsigned num_chunks = 0;
@ -1557,7 +1557,7 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index)
chunks[num_chunks].chunk_data = (uintptr_t)sem_chunk;
num_chunks++;
if (ws->info.has_fw_based_shadowing && acs->mcbp_fw_shadow_chunk.shadow_va) {
if (aws->info.has_fw_based_shadowing && acs->mcbp_fw_shadow_chunk.shadow_va) {
chunks[num_chunks].chunk_id = AMDGPU_CHUNK_ID_CP_GFX_SHADOW;
chunks[num_chunks].length_dw = sizeof(struct drm_amdgpu_cs_chunk_cp_gfx_shadow) / 4;
chunks[num_chunks].chunk_data = (uintptr_t)&acs->mcbp_fw_shadow_chunk;
@ -1599,7 +1599,7 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index)
if (noop && acs->ip_type == AMD_IP_GFX) {
/* Reduce the IB size and fill it with NOP to make it like an empty IB. */
unsigned noop_dw_size = ws->info.ip[AMD_IP_GFX].ib_pad_dw_mask + 1;
unsigned noop_dw_size = aws->info.ip[AMD_IP_GFX].ib_pad_dw_mask + 1;
assert(cs->chunk_ib[IB_MAIN].ib_bytes / 4 >= noop_dw_size);
cs->ib_main_addr[0] = PKT3(PKT3_NOP, noop_dw_size - 2, 0);
@ -1629,7 +1629,7 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index)
if (r == -ENOMEM)
os_time_sleep(1000);
r = amdgpu_cs_submit_raw2(ws->dev, acs->ctx->ctx, 0, num_chunks, chunks, &seq_no);
r = amdgpu_cs_submit_raw2(aws->dev, acs->ctx->ctx, 0, num_chunks, chunks, &seq_no);
} while (r == -ENOMEM);
if (!r) {
@ -1672,7 +1672,7 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index)
if (r || noop)
amdgpu_fence_signalled(cs->fence);
if (unlikely(ws->info.has_fw_based_shadowing && acs->mcbp_fw_shadow_chunk.flags && r == 0))
if (unlikely(aws->info.has_fw_based_shadowing && acs->mcbp_fw_shadow_chunk.flags && r == 0))
acs->mcbp_fw_shadow_chunk.flags = 0;
cs->error_code = r;
@ -1690,25 +1690,25 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index)
/* Regular real BOs. */
for (unsigned i = 0; i < initial_num_real_buffers; i++) {
p_atomic_dec(&buffers[i].bo->num_active_ioctls);
amdgpu_winsys_bo_drop_reference(ws, buffers[i].bo);
amdgpu_winsys_bo_drop_reference(aws, buffers[i].bo);
}
/* Do nothing for slab BOs. */
/* Sparse backing BOs. */
for (unsigned i = num_real_buffers_except_sparse; i < num_buffers; i++)
amdgpu_winsys_bo_drop_reference(ws, buffers[i].bo);
amdgpu_winsys_bo_drop_reference(aws, buffers[i].bo);
} else {
for (unsigned i = 0; i < num_buffers; i++) {
p_atomic_dec(&buffers[i].bo->num_active_ioctls);
amdgpu_winsys_bo_drop_reference(ws, buffers[i].bo);
amdgpu_winsys_bo_drop_reference(aws, buffers[i].bo);
}
}
cs->buffer_lists[list].num_buffers = 0;
}
amdgpu_cs_context_cleanup(ws, cs);
amdgpu_cs_context_cleanup(aws, cs);
}
/* Make sure the previous submission is completed. */
@ -1725,16 +1725,16 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs,
struct pipe_fence_handle **fence)
{
struct amdgpu_cs *cs = amdgpu_cs(rcs);
struct amdgpu_winsys *ws = cs->ws;
struct amdgpu_winsys *aws = cs->aws;
int error_code = 0;
uint32_t ib_pad_dw_mask = ws->info.ip[cs->ip_type].ib_pad_dw_mask;
uint32_t ib_pad_dw_mask = aws->info.ip[cs->ip_type].ib_pad_dw_mask;
rcs->current.max_dw += amdgpu_cs_epilog_dws(cs);
/* Pad the IB according to the mask. */
switch (cs->ip_type) {
case AMD_IP_SDMA:
if (ws->info.gfx_level <= GFX6) {
if (aws->info.gfx_level <= GFX6) {
while (rcs->current.cdw & ib_pad_dw_mask)
radeon_emit(rcs, 0xf0000000); /* NOP packet */
} else {
@ -1744,9 +1744,9 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs,
break;
case AMD_IP_GFX:
case AMD_IP_COMPUTE:
amdgpu_pad_gfx_compute_ib(ws, cs->ip_type, rcs->current.buf, &rcs->current.cdw, 0);
amdgpu_pad_gfx_compute_ib(aws, cs->ip_type, rcs->current.buf, &rcs->current.cdw, 0);
if (cs->ip_type == AMD_IP_GFX)
ws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) * 4;
aws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) * 4;
break;
case AMD_IP_UVD:
case AMD_IP_UVD_ENC:
@ -1780,7 +1780,7 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs,
struct amdgpu_cs_context *cur = cs->csc;
/* Set IB sizes. */
amdgpu_ib_finalize(ws, rcs, &cs->main_ib, cs->ip_type);
amdgpu_ib_finalize(aws, rcs, &cs->main_ib, cs->ip_type);
/* Create a fence. */
amdgpu_fence_reference(&cur->fence, NULL);
@ -1809,7 +1809,7 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs,
cs->cst = cur;
/* Submit. */
util_queue_add_job(&ws->cs_queue, cs, &cs->flush_completed,
util_queue_add_job(&aws->cs_queue, cs, &cs->flush_completed,
cs->uses_alt_fence ? amdgpu_cs_submit_ib<true>
: amdgpu_cs_submit_ib<false>, NULL, 0);
@ -1826,13 +1826,13 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs,
if (flags & RADEON_FLUSH_TOGGLE_SECURE_SUBMISSION)
cs->csc->secure = !cs->csc->secure;
amdgpu_cs_context_cleanup_buffers(ws, cs->csc);
amdgpu_cs_context_cleanup(ws, cs->csc);
amdgpu_cs_context_cleanup_buffers(aws, cs->csc);
amdgpu_cs_context_cleanup(aws, cs->csc);
}
memset(cs->csc->buffer_indices_hashlist, -1, sizeof(cs->buffer_indices_hashlist));
amdgpu_get_new_ib(ws, rcs, &cs->main_ib, cs);
amdgpu_get_new_ib(aws, rcs, &cs->main_ib, cs);
if (cs->preamble_ib_bo) {
amdgpu_cs_add_buffer(rcs, cs->preamble_ib_bo,
@ -1840,9 +1840,9 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs,
}
if (cs->ip_type == AMD_IP_GFX)
ws->num_gfx_IBs++;
aws->num_gfx_IBs++;
else if (cs->ip_type == AMD_IP_SDMA)
ws->num_sdma_IBs++;
aws->num_sdma_IBs++;
return error_code;
}
@ -1856,12 +1856,12 @@ static void amdgpu_cs_destroy(struct radeon_cmdbuf *rcs)
amdgpu_cs_sync_flush(rcs);
util_queue_fence_destroy(&cs->flush_completed);
p_atomic_dec(&cs->ws->num_cs);
radeon_bo_reference(&cs->ws->dummy_sws.base, &cs->preamble_ib_bo, NULL);
radeon_bo_reference(&cs->ws->dummy_sws.base, &cs->main_ib.big_buffer, NULL);
p_atomic_dec(&cs->aws->num_cs);
radeon_bo_reference(&cs->aws->dummy_sws.base, &cs->preamble_ib_bo, NULL);
radeon_bo_reference(&cs->aws->dummy_sws.base, &cs->main_ib.big_buffer, NULL);
FREE(rcs->prev);
amdgpu_destroy_cs_context(cs->ws, &cs->csc1);
amdgpu_destroy_cs_context(cs->ws, &cs->csc2);
amdgpu_destroy_cs_context(cs->aws, &cs->csc1);
amdgpu_destroy_cs_context(cs->aws, &cs->csc2);
amdgpu_fence_reference(&cs->next_fence, NULL);
FREE(cs);
}

8
src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
View file

@ -24,7 +24,7 @@ extern "C" {
struct amdgpu_ctx {
struct pipe_reference reference;
struct amdgpu_winsys *ws;
struct amdgpu_winsys *aws;
amdgpu_context_handle ctx;
amdgpu_bo_handle user_fence_bo;
uint64_t *user_fence_cpu_address_base;
@ -87,7 +87,7 @@ struct amdgpu_cs_context {
struct drm_amdgpu_cs_chunk_ib chunk_ib[IB_NUM];
uint32_t *ib_main_addr; /* the beginning of IB before chaining */
struct amdgpu_winsys *ws;
struct amdgpu_winsys *aws;
/* Buffers. */
struct amdgpu_buffer_list buffer_lists[NUM_BO_LIST_TYPES];
@ -115,7 +115,7 @@ struct amdgpu_cs_context {
struct amdgpu_cs {
struct amdgpu_ib main_ib; /* must be first because this is inherited */
struct amdgpu_winsys *ws;
struct amdgpu_winsys *aws;
struct amdgpu_ctx *ctx;
/*
@ -164,7 +164,7 @@ struct amdgpu_fence {
struct pipe_reference reference;
uint32_t syncobj;
struct amdgpu_winsys *ws;
struct amdgpu_winsys *aws;
/* The following field aren't set for imported fences. */
struct amdgpu_ctx *ctx; /* submission context */

8
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
View file

@ -47,7 +47,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
enum radeon_surf_mode mode,
struct radeon_surf *surf)
{
struct amdgpu_winsys *ws = amdgpu_winsys(rws);
struct amdgpu_winsys *aws = amdgpu_winsys(rws);
int r;
r = amdgpu_surface_sanity(tex);
@ -81,14 +81,14 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
* always use consecutive surface indices when FMASK is allocated between
* them.
*/
config.info.surf_index = &ws->surf_index_color;
config.info.fmask_surf_index = &ws->surf_index_fmask;
config.info.surf_index = &aws->surf_index_color;
config.info.fmask_surf_index = &aws->surf_index_fmask;
if (flags & RADEON_SURF_Z_OR_SBUFFER)
config.info.surf_index = NULL;
/* Use radeon_info from the driver, not the winsys. The driver is allowed to change it. */
return ac_compute_surface(ws->addrlib, info, &config, mode, surf);
return ac_compute_surface(aws->addrlib, info, &config, mode, surf);
}
void amdgpu_surface_init_functions(struct amdgpu_screen_winsys *sws)

134
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
View file

@ -31,78 +31,78 @@ DEBUG_GET_ONCE_BOOL_OPTION(all_bos, "RADEON_ALL_BOS", false)
#endif
/* Helper function to do the ioctls needed for setup and init. */
static bool do_winsys_init(struct amdgpu_winsys *ws,
static bool do_winsys_init(struct amdgpu_winsys *aws,
const struct pipe_screen_config *config,
int fd)
{
if (!ac_query_gpu_info(fd, ws->dev, &ws->info, false))
if (!ac_query_gpu_info(fd, aws->dev, &aws->info, false))
goto fail;
/* TODO: Enable this once the kernel handles it efficiently. */
if (ws->info.has_dedicated_vram)
ws->info.has_local_buffers = false;
if (aws->info.has_dedicated_vram)
aws->info.has_local_buffers = false;
ws->addrlib = ac_addrlib_create(&ws->info, &ws->info.max_alignment);
if (!ws->addrlib) {
aws->addrlib = ac_addrlib_create(&aws->info, &aws->info.max_alignment);
if (!aws->addrlib) {
fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
goto fail;
}
ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL ||
aws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL ||
strstr(debug_get_option("AMD_DEBUG", ""), "check_vm") != NULL;
ws->noop_cs = ws->info.family_overridden || debug_get_bool_option("RADEON_NOOP", false);
aws->noop_cs = aws->info.family_overridden || debug_get_bool_option("RADEON_NOOP", false);
#ifdef DEBUG
ws->debug_all_bos = debug_get_option_all_bos();
aws->debug_all_bos = debug_get_option_all_bos();
#endif
ws->reserve_vmid = strstr(debug_get_option("R600_DEBUG", ""), "reserve_vmid") != NULL ||
aws->reserve_vmid = strstr(debug_get_option("R600_DEBUG", ""), "reserve_vmid") != NULL ||
strstr(debug_get_option("AMD_DEBUG", ""), "reserve_vmid") != NULL ||
strstr(debug_get_option("AMD_DEBUG", ""), "sqtt") != NULL;
ws->zero_all_vram_allocs = strstr(debug_get_option("R600_DEBUG", ""), "zerovram") != NULL ||
aws->zero_all_vram_allocs = strstr(debug_get_option("R600_DEBUG", ""), "zerovram") != NULL ||
driQueryOptionb(config->options, "radeonsi_zerovram");
return true;
fail:
amdgpu_device_deinitialize(ws->dev);
ws->dev = NULL;
amdgpu_device_deinitialize(aws->dev);
aws->dev = NULL;
return false;
}
static void do_winsys_deinit(struct amdgpu_winsys *ws)
static void do_winsys_deinit(struct amdgpu_winsys *aws)
{
if (ws->reserve_vmid)
amdgpu_vm_unreserve_vmid(ws->dev, 0);
if (aws->reserve_vmid)
amdgpu_vm_unreserve_vmid(aws->dev, 0);
for (unsigned i = 0; i < ARRAY_SIZE(ws->queues); i++) {
for (unsigned j = 0; j < ARRAY_SIZE(ws->queues[i].fences); j++)
amdgpu_fence_reference(&ws->queues[i].fences[j], NULL);
for (unsigned i = 0; i < ARRAY_SIZE(aws->queues); i++) {
for (unsigned j = 0; j < ARRAY_SIZE(aws->queues[i].fences); j++)
amdgpu_fence_reference(&aws->queues[i].fences[j], NULL);
amdgpu_ctx_reference(&ws->queues[i].last_ctx, NULL);
amdgpu_ctx_reference(&aws->queues[i].last_ctx, NULL);
}
if (util_queue_is_initialized(&ws->cs_queue))
util_queue_destroy(&ws->cs_queue);
if (util_queue_is_initialized(&aws->cs_queue))
util_queue_destroy(&aws->cs_queue);
simple_mtx_destroy(&ws->bo_fence_lock);
if (ws->bo_slabs.groups)
pb_slabs_deinit(&ws->bo_slabs);
pb_cache_deinit(&ws->bo_cache);
_mesa_hash_table_destroy(ws->bo_export_table, NULL);
simple_mtx_destroy(&ws->sws_list_lock);
simple_mtx_destroy(&aws->bo_fence_lock);
if (aws->bo_slabs.groups)
pb_slabs_deinit(&aws->bo_slabs);
pb_cache_deinit(&aws->bo_cache);
_mesa_hash_table_destroy(aws->bo_export_table, NULL);
simple_mtx_destroy(&aws->sws_list_lock);
#ifdef DEBUG
simple_mtx_destroy(&ws->global_bo_list_lock);
simple_mtx_destroy(&aws->global_bo_list_lock);
#endif
simple_mtx_destroy(&ws->bo_export_table_lock);
simple_mtx_destroy(&aws->bo_export_table_lock);
ac_addrlib_destroy(ws->addrlib);
amdgpu_device_deinitialize(ws->dev);
FREE(ws);
ac_addrlib_destroy(aws->addrlib);
amdgpu_device_deinitialize(aws->dev);
FREE(aws);
}
static void amdgpu_winsys_destroy_locked(struct radeon_winsys *rws, bool locked)
{
struct amdgpu_screen_winsys *sws = amdgpu_screen_winsys(rws);
struct amdgpu_winsys *ws = sws->aws;
struct amdgpu_winsys *aws = sws->aws;
bool destroy;
/* When the reference counter drops to zero, remove the device pointer
@ -114,9 +114,9 @@ static void amdgpu_winsys_destroy_locked(struct radeon_winsys *rws, bool locked)
if (!locked)
simple_mtx_lock(&dev_tab_mutex);
destroy = pipe_reference(&ws->reference, NULL);
destroy = pipe_reference(&aws->reference, NULL);
if (destroy && dev_tab) {
_mesa_hash_table_remove_key(dev_tab, ws->dev);
_mesa_hash_table_remove_key(dev_tab, aws->dev);
if (_mesa_hash_table_num_entries(dev_tab) == 0) {
_mesa_hash_table_destroy(dev_tab, NULL);
dev_tab = NULL;
@ -127,7 +127,7 @@ static void amdgpu_winsys_destroy_locked(struct radeon_winsys *rws, bool locked)
simple_mtx_unlock(&dev_tab_mutex);
if (destroy)
do_winsys_deinit(ws);
do_winsys_deinit(aws);
close(sws->fd);
FREE(rws);
@ -140,9 +140,9 @@ static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
static void amdgpu_winsys_query_info(struct radeon_winsys *rws, struct radeon_info *info)
{
struct amdgpu_winsys *ws = amdgpu_winsys(rws);
struct amdgpu_winsys *aws = amdgpu_winsys(rws);
*info = ws->info;
*info = aws->info;
}
static bool amdgpu_cs_request_feature(struct radeon_cmdbuf *rcs,
@ -155,68 +155,68 @@ static bool amdgpu_cs_request_feature(struct radeon_cmdbuf *rcs,
static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
enum radeon_value_id value)
{
struct amdgpu_winsys *ws = amdgpu_winsys(rws);
struct amdgpu_winsys *aws = amdgpu_winsys(rws);
struct amdgpu_heap_info heap;
uint64_t retval = 0;
switch (value) {
case RADEON_REQUESTED_VRAM_MEMORY:
return ws->allocated_vram;
return aws->allocated_vram;
case RADEON_REQUESTED_GTT_MEMORY:
return ws->allocated_gtt;
return aws->allocated_gtt;
case RADEON_MAPPED_VRAM:
return ws->mapped_vram;
return aws->mapped_vram;
case RADEON_MAPPED_GTT:
return ws->mapped_gtt;
return aws->mapped_gtt;
case RADEON_SLAB_WASTED_VRAM:
return ws->slab_wasted_vram;
return aws->slab_wasted_vram;
case RADEON_SLAB_WASTED_GTT:
return ws->slab_wasted_gtt;
return aws->slab_wasted_gtt;
case RADEON_BUFFER_WAIT_TIME_NS:
return ws->buffer_wait_time;
return aws->buffer_wait_time;
case RADEON_NUM_MAPPED_BUFFERS:
return ws->num_mapped_buffers;
return aws->num_mapped_buffers;
case RADEON_TIMESTAMP:
amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
amdgpu_query_info(aws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
return retval;
case RADEON_NUM_GFX_IBS:
return ws->num_gfx_IBs;
return aws->num_gfx_IBs;
case RADEON_NUM_SDMA_IBS:
return ws->num_sdma_IBs;
return aws->num_sdma_IBs;
case RADEON_GFX_BO_LIST_COUNTER:
return ws->gfx_bo_list_counter;
return aws->gfx_bo_list_counter;
case RADEON_GFX_IB_SIZE_COUNTER:
return ws->gfx_ib_size_counter;
return aws->gfx_ib_size_counter;
case RADEON_NUM_BYTES_MOVED:
amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval);
amdgpu_query_info(aws->dev, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval);
return retval;
case RADEON_NUM_EVICTIONS:
amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_EVICTIONS, 8, &retval);
amdgpu_query_info(aws->dev, AMDGPU_INFO_NUM_EVICTIONS, 8, &retval);
return retval;
case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS, 8, &retval);
amdgpu_query_info(aws->dev, AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS, 8, &retval);
return retval;
case RADEON_VRAM_USAGE:
amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap);
amdgpu_query_heap_info(aws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap);
return heap.heap_usage;
case RADEON_VRAM_VIS_USAGE:
amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
amdgpu_query_heap_info(aws->dev, AMDGPU_GEM_DOMAIN_VRAM,
AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &heap);
return heap.heap_usage;
case RADEON_GTT_USAGE:
amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &heap);
amdgpu_query_heap_info(aws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &heap);
return heap.heap_usage;
case RADEON_GPU_TEMPERATURE:
amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GPU_TEMP, 4, &retval);
amdgpu_query_sensor_info(aws->dev, AMDGPU_INFO_SENSOR_GPU_TEMP, 4, &retval);
return retval;
case RADEON_CURRENT_SCLK:
amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_SCLK, 4, &retval);
amdgpu_query_sensor_info(aws->dev, AMDGPU_INFO_SENSOR_GFX_SCLK, 4, &retval);
return retval;
case RADEON_CURRENT_MCLK:
amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_MCLK, 4, &retval);
amdgpu_query_sensor_info(aws->dev, AMDGPU_INFO_SENSOR_GFX_MCLK, 4, &retval);
return retval;
case RADEON_CS_THREAD_TIME:
return util_queue_get_thread_time_nano(&ws->cs_queue, 0);
return util_queue_get_thread_time_nano(&aws->cs_queue, 0);
}
return 0;
}
@ -225,9 +225,9 @@ static bool amdgpu_read_registers(struct radeon_winsys *rws,
unsigned reg_offset,
unsigned num_registers, uint32_t *out)
{
struct amdgpu_winsys *ws = amdgpu_winsys(rws);
struct amdgpu_winsys *aws = amdgpu_winsys(rws);
return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
return amdgpu_read_mm_registers(aws->dev, reg_offset / 4, num_registers,
0xffffffff, 0, out) == 0;
}
@ -273,9 +273,9 @@ static bool amdgpu_winsys_unref(struct radeon_winsys *rws)
static void amdgpu_pin_threads_to_L3_cache(struct radeon_winsys *rws,
unsigned cpu)
{
struct amdgpu_winsys *ws = amdgpu_winsys(rws);
struct amdgpu_winsys *aws = amdgpu_winsys(rws);
util_thread_sched_apply_policy(ws->cs_queue.threads[0],
util_thread_sched_apply_policy(aws->cs_queue.threads[0],
UTIL_THREAD_DRIVER_SUBMIT, cpu, NULL);
}