From 5b6c0fdc97edcbec345250203e744082787aebc0 Mon Sep 17 00:00:00 2001 From: Yogesh Mohan Marimuthu Date: Mon, 4 Mar 2024 10:05:44 +0530 Subject: [PATCH] winsys/amdgpu: aws instead of ws for amdgpu_winsys MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Marek Olšák Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 344 +++++++++--------- src/gallium/winsys/amdgpu/drm/amdgpu_bo.h | 30 +- src/gallium/winsys/amdgpu/drm/amdgpu_cs.cpp | 244 ++++++------- src/gallium/winsys/amdgpu/drm/amdgpu_cs.h | 8 +- .../winsys/amdgpu/drm/amdgpu_surface.c | 8 +- src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 134 +++---- 6 files changed, 384 insertions(+), 384 deletions(-) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c index d6094e4e497..adbffa7689a 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c @@ -31,7 +31,7 @@ struct amdgpu_sparse_backing_chunk { uint32_t begin, end; }; -static bool amdgpu_bo_fence_wait(struct amdgpu_winsys *ws, +static bool amdgpu_bo_fence_wait(struct amdgpu_winsys *aws, struct pipe_fence_handle **fence, uint64_t timeout, int64_t abs_timeout) { @@ -39,7 +39,7 @@ static bool amdgpu_bo_fence_wait(struct amdgpu_winsys *ws, bool idle = amdgpu_fence_wait(*fence, 0, false); if (!idle) { - simple_mtx_unlock(&ws->bo_fence_lock); + simple_mtx_unlock(&aws->bo_fence_lock); return false; /* busy */ } @@ -50,7 +50,7 @@ static bool amdgpu_bo_fence_wait(struct amdgpu_winsys *ws, amdgpu_fence_reference(&tmp_fence, *fence); /* While waiting, unlock the mutex. */ - simple_mtx_unlock(&ws->bo_fence_lock); + simple_mtx_unlock(&aws->bo_fence_lock); bool idle = amdgpu_fence_wait(tmp_fence, abs_timeout, true); if (!idle) { @@ -58,7 +58,7 @@ static bool amdgpu_bo_fence_wait(struct amdgpu_winsys *ws, return false; /* busy */ } - simple_mtx_lock(&ws->bo_fence_lock); + simple_mtx_lock(&aws->bo_fence_lock); /* It's idle. Remove it from the ring to skip checking it again later. */ if (tmp_fence == *fence) amdgpu_fence_reference(fence, NULL); @@ -72,7 +72,7 @@ static bool amdgpu_bo_wait(struct radeon_winsys *rws, struct pb_buffer_lean *_buf, uint64_t timeout, unsigned usage) { - struct amdgpu_winsys *ws = amdgpu_winsys(rws); + struct amdgpu_winsys *aws = amdgpu_winsys(rws); struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf); int64_t abs_timeout = 0; @@ -111,14 +111,14 @@ static bool amdgpu_bo_wait(struct radeon_winsys *rws, return !buffer_busy; } - simple_mtx_lock(&ws->bo_fence_lock); + simple_mtx_lock(&aws->bo_fence_lock); u_foreach_bit(i, bo->fences.valid_fence_mask) { - struct pipe_fence_handle **fence = get_fence_from_ring(ws, &bo->fences, i); + struct pipe_fence_handle **fence = get_fence_from_ring(aws, &bo->fences, i); if (fence) { /* This also unlocks the mutex on failure. */ - if (!amdgpu_bo_fence_wait(ws, fence, timeout, abs_timeout)) + if (!amdgpu_bo_fence_wait(aws, fence, timeout, abs_timeout)) return false; } @@ -128,11 +128,11 @@ static bool amdgpu_bo_wait(struct radeon_winsys *rws, /* Also wait for alt_fence. */ if (bo->alt_fence) { /* This also unlocks the mutex on failure. */ - if (!amdgpu_bo_fence_wait(ws, &bo->alt_fence, timeout, abs_timeout)) + if (!amdgpu_bo_fence_wait(aws, &bo->alt_fence, timeout, abs_timeout)) return false; } - simple_mtx_unlock(&ws->bo_fence_lock); + simple_mtx_unlock(&aws->bo_fence_lock); return true; /* idle */ } @@ -164,20 +164,20 @@ static void amdgpu_bo_remove_fences(struct amdgpu_winsys_bo *bo) amdgpu_fence_reference(&bo->alt_fence, NULL); } -void amdgpu_bo_destroy(struct amdgpu_winsys *ws, struct pb_buffer_lean *_buf) +void amdgpu_bo_destroy(struct amdgpu_winsys *aws, struct pb_buffer_lean *_buf) { struct amdgpu_bo_real *bo = get_real_bo(amdgpu_winsys_bo(_buf)); struct amdgpu_screen_winsys *sws_iter; - simple_mtx_lock(&ws->bo_export_table_lock); + simple_mtx_lock(&aws->bo_export_table_lock); /* amdgpu_bo_from_handle might have revived the bo */ if (p_atomic_read(&bo->b.base.reference.count)) { - simple_mtx_unlock(&ws->bo_export_table_lock); + simple_mtx_unlock(&aws->bo_export_table_lock); return; } - _mesa_hash_table_remove_key(ws->bo_export_table, bo->bo_handle); + _mesa_hash_table_remove_key(aws->bo_export_table, bo->bo_handle); if (bo->b.base.placement & RADEON_DOMAIN_VRAM_GTT) { amdgpu_bo_va_op(bo->bo_handle, 0, bo->b.base.size, @@ -185,28 +185,28 @@ void amdgpu_bo_destroy(struct amdgpu_winsys *ws, struct pb_buffer_lean *_buf) amdgpu_va_range_free(bo->va_handle); } - simple_mtx_unlock(&ws->bo_export_table_lock); + simple_mtx_unlock(&aws->bo_export_table_lock); if (!bo->is_user_ptr && bo->cpu_ptr) { bo->cpu_ptr = NULL; - amdgpu_bo_unmap(&ws->dummy_sws.base, &bo->b.base); + amdgpu_bo_unmap(&aws->dummy_sws.base, &bo->b.base); } assert(bo->is_user_ptr || bo->map_count == 0); amdgpu_bo_free(bo->bo_handle); #ifdef DEBUG - if (ws->debug_all_bos) { - simple_mtx_lock(&ws->global_bo_list_lock); + if (aws->debug_all_bos) { + simple_mtx_lock(&aws->global_bo_list_lock); list_del(&bo->global_list_item); - ws->num_buffers--; - simple_mtx_unlock(&ws->global_bo_list_lock); + aws->num_buffers--; + simple_mtx_unlock(&aws->global_bo_list_lock); } #endif /* Close all KMS handles retrieved for other DRM file descriptions */ - simple_mtx_lock(&ws->sws_list_lock); - for (sws_iter = ws->sws_list; sws_iter; sws_iter = sws_iter->next) { + simple_mtx_lock(&aws->sws_list_lock); + for (sws_iter = aws->sws_list; sws_iter; sws_iter = sws_iter->next) { struct hash_entry *entry; if (!sws_iter->kms_handles) @@ -220,14 +220,14 @@ void amdgpu_bo_destroy(struct amdgpu_winsys *ws, struct pb_buffer_lean *_buf) _mesa_hash_table_remove(sws_iter->kms_handles, entry); } } - simple_mtx_unlock(&ws->sws_list_lock); + simple_mtx_unlock(&aws->sws_list_lock); amdgpu_bo_remove_fences(&bo->b); if (bo->b.base.placement & RADEON_DOMAIN_VRAM) - ws->allocated_vram -= align64(bo->b.base.size, ws->info.gart_page_size); + aws->allocated_vram -= align64(bo->b.base.size, aws->info.gart_page_size); else if (bo->b.base.placement & RADEON_DOMAIN_GTT) - ws->allocated_gtt -= align64(bo->b.base.size, ws->info.gart_page_size); + aws->allocated_gtt -= align64(bo->b.base.size, aws->info.gart_page_size); simple_mtx_destroy(&bo->map_lock); FREE(bo); @@ -235,33 +235,33 @@ void amdgpu_bo_destroy(struct amdgpu_winsys *ws, struct pb_buffer_lean *_buf) static void amdgpu_bo_destroy_or_cache(struct radeon_winsys *rws, struct pb_buffer_lean *_buf) { - struct amdgpu_winsys *ws = amdgpu_winsys(rws); + struct amdgpu_winsys *aws = amdgpu_winsys(rws); struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf); assert(is_real_bo(bo)); /* slab buffers have a separate vtbl */ if (bo->type >= AMDGPU_BO_REAL_REUSABLE) - pb_cache_add_buffer(&ws->bo_cache, &((struct amdgpu_bo_real_reusable*)bo)->cache_entry); + pb_cache_add_buffer(&aws->bo_cache, &((struct amdgpu_bo_real_reusable*)bo)->cache_entry); else - amdgpu_bo_destroy(ws, _buf); + amdgpu_bo_destroy(aws, _buf); } -static void amdgpu_clean_up_buffer_managers(struct amdgpu_winsys *ws) +static void amdgpu_clean_up_buffer_managers(struct amdgpu_winsys *aws) { - pb_slabs_reclaim(&ws->bo_slabs); - pb_cache_release_all_buffers(&ws->bo_cache); + pb_slabs_reclaim(&aws->bo_slabs); + pb_cache_release_all_buffers(&aws->bo_cache); } static bool amdgpu_bo_do_map(struct radeon_winsys *rws, struct amdgpu_bo_real *bo, void **cpu) { - struct amdgpu_winsys *ws = amdgpu_winsys(rws); + struct amdgpu_winsys *aws = amdgpu_winsys(rws); assert(!bo->is_user_ptr); int r = amdgpu_bo_cpu_map(bo->bo_handle, cpu); if (r) { /* Clean up buffer managers and try again. */ - amdgpu_clean_up_buffer_managers(ws); + amdgpu_clean_up_buffer_managers(aws); r = amdgpu_bo_cpu_map(bo->bo_handle, cpu); if (r) return false; @@ -269,10 +269,10 @@ static bool amdgpu_bo_do_map(struct radeon_winsys *rws, struct amdgpu_bo_real *b if (p_atomic_inc_return(&bo->map_count) == 1) { if (bo->b.base.placement & RADEON_DOMAIN_VRAM) - ws->mapped_vram += bo->b.base.size; + aws->mapped_vram += bo->b.base.size; else if (bo->b.base.placement & RADEON_DOMAIN_GTT) - ws->mapped_gtt += bo->b.base.size; - ws->num_mapped_buffers++; + aws->mapped_gtt += bo->b.base.size; + aws->num_mapped_buffers++; } return true; @@ -283,7 +283,7 @@ void *amdgpu_bo_map(struct radeon_winsys *rws, struct radeon_cmdbuf *rcs, enum pipe_map_flags usage) { - struct amdgpu_winsys *ws = amdgpu_winsys(rws); + struct amdgpu_winsys *aws = amdgpu_winsys(rws); struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf; struct amdgpu_bo_real *real; struct amdgpu_cs *cs = rcs ? amdgpu_cs(rcs) : NULL; @@ -367,7 +367,7 @@ void *amdgpu_bo_map(struct radeon_winsys *rws, RADEON_USAGE_READWRITE); } - ws->buffer_wait_time += os_time_get_nano() - time; + aws->buffer_wait_time += os_time_get_nano() - time; } } @@ -412,7 +412,7 @@ void *amdgpu_bo_map(struct radeon_winsys *rws, void amdgpu_bo_unmap(struct radeon_winsys *rws, struct pb_buffer_lean *buf) { - struct amdgpu_winsys *ws = amdgpu_winsys(rws); + struct amdgpu_winsys *aws = amdgpu_winsys(rws); struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf; struct amdgpu_bo_real *real; @@ -429,35 +429,35 @@ void amdgpu_bo_unmap(struct radeon_winsys *rws, struct pb_buffer_lean *buf) "too many unmaps or forgot RADEON_MAP_TEMPORARY flag"); if (real->b.base.placement & RADEON_DOMAIN_VRAM) - ws->mapped_vram -= real->b.base.size; + aws->mapped_vram -= real->b.base.size; else if (real->b.base.placement & RADEON_DOMAIN_GTT) - ws->mapped_gtt -= real->b.base.size; - ws->num_mapped_buffers--; + aws->mapped_gtt -= real->b.base.size; + aws->num_mapped_buffers--; } amdgpu_bo_cpu_unmap(real->bo_handle); } -static void amdgpu_add_buffer_to_global_list(struct amdgpu_winsys *ws, struct amdgpu_bo_real *bo) +static void amdgpu_add_buffer_to_global_list(struct amdgpu_winsys *aws, struct amdgpu_bo_real *bo) { #ifdef DEBUG - if (ws->debug_all_bos) { - simple_mtx_lock(&ws->global_bo_list_lock); - list_addtail(&bo->global_list_item, &ws->global_bo_list); - ws->num_buffers++; - simple_mtx_unlock(&ws->global_bo_list_lock); + if (aws->debug_all_bos) { + simple_mtx_lock(&aws->global_bo_list_lock); + list_addtail(&bo->global_list_item, &aws->global_bo_list); + aws->num_buffers++; + simple_mtx_unlock(&aws->global_bo_list_lock); } #endif } -static unsigned amdgpu_get_optimal_alignment(struct amdgpu_winsys *ws, +static unsigned amdgpu_get_optimal_alignment(struct amdgpu_winsys *aws, uint64_t size, unsigned alignment) { /* Increase the alignment for faster address translation and better memory * access pattern. */ - if (size >= ws->info.pte_fragment_size) { - alignment = MAX2(alignment, ws->info.pte_fragment_size); + if (size >= aws->info.pte_fragment_size) { + alignment = MAX2(alignment, aws->info.pte_fragment_size); } else if (size) { unsigned msb = util_last_bit(size); @@ -466,7 +466,7 @@ static unsigned amdgpu_get_optimal_alignment(struct amdgpu_winsys *ws, return alignment; } -static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *ws, +static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *aws, uint64_t size, unsigned alignment, enum radeon_bo_domain initial_domain, @@ -485,7 +485,7 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *ws, RADEON_DOMAIN_GDS | RADEON_DOMAIN_OA)) == 1); - alignment = amdgpu_get_optimal_alignment(ws, size, alignment); + alignment = amdgpu_get_optimal_alignment(aws, size, alignment); if (heap >= 0 && flags & RADEON_FLAG_NO_INTERPROCESS_SHARING) { struct amdgpu_bo_real_reusable *new_bo; @@ -500,7 +500,7 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *ws, return NULL; bo = &new_bo->b; - pb_cache_init_entry(&ws->bo_cache, &new_bo->cache_entry, &bo->b.base, heap); + pb_cache_init_entry(&aws->bo_cache, &new_bo->cache_entry, &bo->b.base, heap); bo->b.type = slab_backing ? AMDGPU_BO_REAL_REUSABLE_SLAB : AMDGPU_BO_REAL_REUSABLE; } else { bo = CALLOC_STRUCT(amdgpu_bo_real); @@ -521,7 +521,7 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *ws, * shared with the OS, allow VRAM placements too. The idea is not to use * VRAM usefully, but to use it so that it's not unused and wasted. */ - if (!ws->info.has_dedicated_vram) + if (!aws->info.has_dedicated_vram) request.preferred_heap |= AMDGPU_GEM_DOMAIN_GTT; } @@ -538,28 +538,28 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *ws, request.flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC; if (flags & RADEON_FLAG_DISCARDABLE && - ws->info.drm_minor >= 47) + aws->info.drm_minor >= 47) request.flags |= AMDGPU_GEM_CREATE_DISCARDABLE; - if (ws->zero_all_vram_allocs && + if (aws->zero_all_vram_allocs && (request.preferred_heap & AMDGPU_GEM_DOMAIN_VRAM)) request.flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; if ((flags & RADEON_FLAG_ENCRYPTED) && - ws->info.has_tmz_support) { + aws->info.has_tmz_support) { request.flags |= AMDGPU_GEM_CREATE_ENCRYPTED; if (!(flags & RADEON_FLAG_DRIVER_INTERNAL)) { struct amdgpu_screen_winsys *sws_iter; - simple_mtx_lock(&ws->sws_list_lock); - for (sws_iter = ws->sws_list; sws_iter; sws_iter = sws_iter->next) { + simple_mtx_lock(&aws->sws_list_lock); + for (sws_iter = aws->sws_list; sws_iter; sws_iter = sws_iter->next) { *((bool*) &sws_iter->base.uses_secure_bos) = true; } - simple_mtx_unlock(&ws->sws_list_lock); + simple_mtx_unlock(&aws->sws_list_lock); } } - r = amdgpu_bo_alloc(ws->dev, &request, &buf_handle); + r = amdgpu_bo_alloc(aws->dev, &request, &buf_handle); if (r) { fprintf(stderr, "amdgpu: Failed to allocate a buffer:\n"); fprintf(stderr, "amdgpu: size : %"PRIu64" bytes\n", size); @@ -570,9 +570,9 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *ws, } if (initial_domain & RADEON_DOMAIN_VRAM_GTT) { - unsigned va_gap_size = ws->check_vm ? MAX2(4 * alignment, 64 * 1024) : 0; + unsigned va_gap_size = aws->check_vm ? MAX2(4 * alignment, 64 * 1024) : 0; - r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general, + r = amdgpu_va_range_alloc(aws->dev, amdgpu_gpu_va_range_general, size + va_gap_size, alignment, 0, &va, &va_handle, (flags & RADEON_FLAG_32BIT ? AMDGPU_VA_RANGE_32_BIT : 0) | @@ -589,7 +589,7 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *ws, if (flags & RADEON_FLAG_GL2_BYPASS) vm_flags |= AMDGPU_VM_MTYPE_UC; - r = amdgpu_bo_va_op_raw(ws->dev, buf_handle, 0, size, va, vm_flags, + r = amdgpu_bo_va_op_raw(aws->dev, buf_handle, 0, size, va, vm_flags, AMDGPU_VA_OP_MAP); if (r) goto error_va_map; @@ -601,17 +601,17 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *ws, bo->b.base.alignment_log2 = util_logbase2(alignment); bo->b.base.usage = flags; bo->b.base.size = size; - bo->b.unique_id = __sync_fetch_and_add(&ws->next_bo_unique_id, 1); + bo->b.unique_id = __sync_fetch_and_add(&aws->next_bo_unique_id, 1); bo->bo_handle = buf_handle; bo->va_handle = va_handle; if (initial_domain & RADEON_DOMAIN_VRAM) - ws->allocated_vram += align64(size, ws->info.gart_page_size); + aws->allocated_vram += align64(size, aws->info.gart_page_size); else if (initial_domain & RADEON_DOMAIN_GTT) - ws->allocated_gtt += align64(size, ws->info.gart_page_size); + aws->allocated_gtt += align64(size, aws->info.gart_page_size); amdgpu_bo_export(bo->bo_handle, amdgpu_bo_handle_type_kms, &bo->kms_handle); - amdgpu_add_buffer_to_global_list(ws, bo); + amdgpu_add_buffer_to_global_list(aws, bo); return &bo->b; @@ -626,9 +626,9 @@ error_bo_alloc: return NULL; } -bool amdgpu_bo_can_reclaim(struct amdgpu_winsys *ws, struct pb_buffer_lean *_buf) +bool amdgpu_bo_can_reclaim(struct amdgpu_winsys *aws, struct pb_buffer_lean *_buf) { - return amdgpu_bo_wait(&ws->dummy_sws.base, _buf, 0, RADEON_USAGE_READWRITE); + return amdgpu_bo_wait(&aws->dummy_sws.base, _buf, 0, RADEON_USAGE_READWRITE); } bool amdgpu_bo_can_reclaim_slab(void *priv, struct pb_slab_entry *entry) @@ -638,41 +638,41 @@ bool amdgpu_bo_can_reclaim_slab(void *priv, struct pb_slab_entry *entry) return amdgpu_bo_can_reclaim(priv, &bo->b.base); } -static unsigned get_slab_wasted_size(struct amdgpu_winsys *ws, struct amdgpu_bo_slab_entry *bo) +static unsigned get_slab_wasted_size(struct amdgpu_winsys *aws, struct amdgpu_bo_slab_entry *bo) { assert(bo->b.base.size <= bo->entry.slab->entry_size); assert(bo->b.base.size < (1 << bo->b.base.alignment_log2) || - bo->b.base.size < 1 << ws->bo_slabs.min_order || + bo->b.base.size < 1 << aws->bo_slabs.min_order || bo->b.base.size > bo->entry.slab->entry_size / 2); return bo->entry.slab->entry_size - bo->b.base.size; } static void amdgpu_bo_slab_destroy(struct radeon_winsys *rws, struct pb_buffer_lean *_buf) { - struct amdgpu_winsys *ws = amdgpu_winsys(rws); + struct amdgpu_winsys *aws = amdgpu_winsys(rws); struct amdgpu_bo_slab_entry *bo = get_slab_entry_bo(amdgpu_winsys_bo(_buf)); if (bo->b.base.placement & RADEON_DOMAIN_VRAM) - ws->slab_wasted_vram -= get_slab_wasted_size(ws, bo); + aws->slab_wasted_vram -= get_slab_wasted_size(aws, bo); else - ws->slab_wasted_gtt -= get_slab_wasted_size(ws, bo); + aws->slab_wasted_gtt -= get_slab_wasted_size(aws, bo); - pb_slab_free(&ws->bo_slabs, &bo->entry); + pb_slab_free(&aws->bo_slabs, &bo->entry); } /* Return the power of two size of a slab entry matching the input size. */ -static unsigned get_slab_pot_entry_size(struct amdgpu_winsys *ws, unsigned size) +static unsigned get_slab_pot_entry_size(struct amdgpu_winsys *aws, unsigned size) { unsigned entry_size = util_next_power_of_two(size); - unsigned min_entry_size = 1 << ws->bo_slabs.min_order; + unsigned min_entry_size = 1 << aws->bo_slabs.min_order; return MAX2(entry_size, min_entry_size); } /* Return the slab entry alignment. */ -static unsigned get_slab_entry_alignment(struct amdgpu_winsys *ws, unsigned size) +static unsigned get_slab_entry_alignment(struct amdgpu_winsys *aws, unsigned size) { - unsigned entry_size = get_slab_pot_entry_size(ws, size); + unsigned entry_size = get_slab_pot_entry_size(aws, size); if (size <= entry_size * 3 / 4) return entry_size / 4; @@ -683,12 +683,12 @@ static unsigned get_slab_entry_alignment(struct amdgpu_winsys *ws, unsigned size struct pb_slab *amdgpu_bo_slab_alloc(void *priv, unsigned heap, unsigned entry_size, unsigned group_index) { - struct amdgpu_winsys *ws = priv; + struct amdgpu_winsys *aws = priv; enum radeon_bo_domain domains = radeon_domain_from_heap(heap); enum radeon_bo_flag flags = radeon_flags_from_heap(heap); /* Determine the slab buffer size. */ - unsigned max_entry_size = 1 << (ws->bo_slabs.min_order + ws->bo_slabs.num_orders - 1); + unsigned max_entry_size = 1 << (aws->bo_slabs.min_order + aws->bo_slabs.num_orders - 1); assert(entry_size <= max_entry_size); @@ -713,14 +713,14 @@ struct pb_slab *amdgpu_bo_slab_alloc(void *priv, unsigned heap, unsigned entry_s /* The largest slab should have the same size as the PTE fragment * size to get faster address translation. */ - slab_size = MAX2(slab_size, ws->info.pte_fragment_size); + slab_size = MAX2(slab_size, aws->info.pte_fragment_size); flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING | RADEON_FLAG_NO_SUBALLOC | RADEON_FLAG_WINSYS_SLAB_BACKING; struct amdgpu_bo_real_reusable_slab *slab_bo = - (struct amdgpu_bo_real_reusable_slab*)amdgpu_bo_create(ws, slab_size, slab_size, + (struct amdgpu_bo_real_reusable_slab*)amdgpu_bo_create(aws, slab_size, slab_size, domains, flags); if (!slab_bo) return NULL; @@ -748,7 +748,7 @@ struct pb_slab *amdgpu_bo_slab_alloc(void *priv, unsigned heap, unsigned entry_s struct amdgpu_bo_slab_entry *bo = &slab_bo->entries[i]; bo->b.base.placement = domains; - bo->b.base.alignment_log2 = util_logbase2(get_slab_entry_alignment(ws, entry_size)); + bo->b.base.alignment_log2 = util_logbase2(get_slab_entry_alignment(aws, entry_size)); bo->b.base.size = entry_size; bo->b.type = AMDGPU_BO_SLAB_ENTRY; @@ -759,33 +759,33 @@ struct pb_slab *amdgpu_bo_slab_alloc(void *priv, unsigned heap, unsigned entry_s /* Wasted alignment due to slabs with 3/4 allocations being aligned to a power of two. */ assert(slab_bo->slab.num_entries * entry_size <= slab_size); if (domains & RADEON_DOMAIN_VRAM) - ws->slab_wasted_vram += slab_size - slab_bo->slab.num_entries * entry_size; + aws->slab_wasted_vram += slab_size - slab_bo->slab.num_entries * entry_size; else - ws->slab_wasted_gtt += slab_size - slab_bo->slab.num_entries * entry_size; + aws->slab_wasted_gtt += slab_size - slab_bo->slab.num_entries * entry_size; return &slab_bo->slab; fail: - amdgpu_winsys_bo_reference(ws, (struct amdgpu_winsys_bo**)&slab_bo, NULL); + amdgpu_winsys_bo_reference(aws, (struct amdgpu_winsys_bo**)&slab_bo, NULL); return NULL; } -void amdgpu_bo_slab_free(struct amdgpu_winsys *ws, struct pb_slab *slab) +void amdgpu_bo_slab_free(struct amdgpu_winsys *aws, struct pb_slab *slab) { struct amdgpu_bo_real_reusable_slab *bo = get_bo_from_slab(slab); unsigned slab_size = bo->b.b.b.base.size; assert(bo->slab.num_entries * bo->slab.entry_size <= slab_size); if (bo->b.b.b.base.placement & RADEON_DOMAIN_VRAM) - ws->slab_wasted_vram -= slab_size - bo->slab.num_entries * bo->slab.entry_size; + aws->slab_wasted_vram -= slab_size - bo->slab.num_entries * bo->slab.entry_size; else - ws->slab_wasted_gtt -= slab_size - bo->slab.num_entries * bo->slab.entry_size; + aws->slab_wasted_gtt -= slab_size - bo->slab.num_entries * bo->slab.entry_size; for (unsigned i = 0; i < bo->slab.num_entries; ++i) amdgpu_bo_remove_fences(&bo->entries[i].b); os_free_aligned(bo->entries); - amdgpu_winsys_bo_reference(ws, (struct amdgpu_winsys_bo**)&bo, NULL); + amdgpu_winsys_bo_reference(aws, (struct amdgpu_winsys_bo**)&bo, NULL); } #if DEBUG_SPARSE_COMMITS @@ -849,7 +849,7 @@ sparse_dump(struct amdgpu_bo_sparse *bo, const char *func) * which will be reflected by a change to *pnum_pages. */ static struct amdgpu_sparse_backing * -sparse_backing_alloc(struct amdgpu_winsys *ws, struct amdgpu_bo_sparse *bo, +sparse_backing_alloc(struct amdgpu_winsys *aws, struct amdgpu_bo_sparse *bo, uint32_t *pstart_page, uint32_t *pnum_pages) { struct amdgpu_sparse_backing *best_backing; @@ -898,7 +898,7 @@ sparse_backing_alloc(struct amdgpu_winsys *ws, struct amdgpu_bo_sparse *bo, bo->b.base.size - (uint64_t)bo->num_backing_pages * RADEON_SPARSE_PAGE_SIZE); size = MAX2(size, RADEON_SPARSE_PAGE_SIZE); - buf = amdgpu_bo_create(ws, size, RADEON_SPARSE_PAGE_SIZE, + buf = amdgpu_bo_create(aws, size, RADEON_SPARSE_PAGE_SIZE, bo->b.base.placement, (bo->b.base.usage & ~RADEON_FLAG_SPARSE & /* Set the interprocess sharing flag to disable pb_cache because @@ -940,20 +940,20 @@ sparse_backing_alloc(struct amdgpu_winsys *ws, struct amdgpu_bo_sparse *bo, } static void -sparse_free_backing_buffer(struct amdgpu_winsys *ws, struct amdgpu_bo_sparse *bo, +sparse_free_backing_buffer(struct amdgpu_winsys *aws, struct amdgpu_bo_sparse *bo, struct amdgpu_sparse_backing *backing) { bo->num_backing_pages -= backing->bo->b.base.size / RADEON_SPARSE_PAGE_SIZE; /* Add fences from bo to backing->bo. */ - simple_mtx_lock(&ws->bo_fence_lock); + simple_mtx_lock(&aws->bo_fence_lock); u_foreach_bit(i, bo->b.fences.valid_fence_mask) { - add_seq_no_to_list(ws, &backing->bo->b.fences, i, bo->b.fences.seq_no[i]); + add_seq_no_to_list(aws, &backing->bo->b.fences, i, bo->b.fences.seq_no[i]); } - simple_mtx_unlock(&ws->bo_fence_lock); + simple_mtx_unlock(&aws->bo_fence_lock); list_del(&backing->list); - amdgpu_winsys_bo_reference(ws, (struct amdgpu_winsys_bo**)&backing->bo, NULL); + amdgpu_winsys_bo_reference(aws, (struct amdgpu_winsys_bo**)&backing->bo, NULL); FREE(backing->chunks); FREE(backing); } @@ -963,7 +963,7 @@ sparse_free_backing_buffer(struct amdgpu_winsys *ws, struct amdgpu_bo_sparse *bo * free structure. */ static bool -sparse_backing_free(struct amdgpu_winsys *ws, struct amdgpu_bo_sparse *bo, +sparse_backing_free(struct amdgpu_winsys *aws, struct amdgpu_bo_sparse *bo, struct amdgpu_sparse_backing *backing, uint32_t start_page, uint32_t num_pages) { @@ -1018,18 +1018,18 @@ sparse_backing_free(struct amdgpu_winsys *ws, struct amdgpu_bo_sparse *bo, if (backing->num_chunks == 1 && backing->chunks[0].begin == 0 && backing->chunks[0].end == backing->bo->b.base.size / RADEON_SPARSE_PAGE_SIZE) - sparse_free_backing_buffer(ws, bo, backing); + sparse_free_backing_buffer(aws, bo, backing); return true; } static void amdgpu_bo_sparse_destroy(struct radeon_winsys *rws, struct pb_buffer_lean *_buf) { - struct amdgpu_winsys *ws = amdgpu_winsys(rws); + struct amdgpu_winsys *aws = amdgpu_winsys(rws); struct amdgpu_bo_sparse *bo = get_sparse_bo(amdgpu_winsys_bo(_buf)); int r; - r = amdgpu_bo_va_op_raw(ws->dev, NULL, 0, + r = amdgpu_bo_va_op_raw(aws->dev, NULL, 0, (uint64_t)bo->num_va_pages * RADEON_SPARSE_PAGE_SIZE, amdgpu_va_get_start_addr(bo->va_handle), 0, AMDGPU_VA_OP_CLEAR); if (r) { @@ -1037,7 +1037,7 @@ static void amdgpu_bo_sparse_destroy(struct radeon_winsys *rws, struct pb_buffer } while (!list_is_empty(&bo->backing)) { - sparse_free_backing_buffer(ws, bo, + sparse_free_backing_buffer(aws, bo, container_of(bo->backing.next, struct amdgpu_sparse_backing, list)); } @@ -1049,7 +1049,7 @@ static void amdgpu_bo_sparse_destroy(struct radeon_winsys *rws, struct pb_buffer } static struct pb_buffer_lean * -amdgpu_bo_sparse_create(struct amdgpu_winsys *ws, uint64_t size, +amdgpu_bo_sparse_create(struct amdgpu_winsys *aws, uint64_t size, enum radeon_bo_domain domain, enum radeon_bo_flag flags) { @@ -1075,7 +1075,7 @@ amdgpu_bo_sparse_create(struct amdgpu_winsys *ws, uint64_t size, bo->b.base.alignment_log2 = util_logbase2(RADEON_SPARSE_PAGE_SIZE); bo->b.base.usage = flags; bo->b.base.size = size; - bo->b.unique_id = __sync_fetch_and_add(&ws->next_bo_unique_id, 1); + bo->b.unique_id = __sync_fetch_and_add(&aws->next_bo_unique_id, 1); bo->b.type = AMDGPU_BO_SPARSE; bo->num_va_pages = DIV_ROUND_UP(size, RADEON_SPARSE_PAGE_SIZE); @@ -1087,16 +1087,16 @@ amdgpu_bo_sparse_create(struct amdgpu_winsys *ws, uint64_t size, /* For simplicity, we always map a multiple of the page size. */ map_size = align64(size, RADEON_SPARSE_PAGE_SIZE); - va_gap_size = ws->check_vm ? 4 * RADEON_SPARSE_PAGE_SIZE : 0; + va_gap_size = aws->check_vm ? 4 * RADEON_SPARSE_PAGE_SIZE : 0; uint64_t gpu_address; - r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general, + r = amdgpu_va_range_alloc(aws->dev, amdgpu_gpu_va_range_general, map_size + va_gap_size, RADEON_SPARSE_PAGE_SIZE, 0, &gpu_address, &bo->va_handle, AMDGPU_VA_RANGE_HIGH); if (r) goto error_va_alloc; - r = amdgpu_bo_va_op_raw(ws->dev, NULL, 0, map_size, gpu_address, + r = amdgpu_bo_va_op_raw(aws->dev, NULL, 0, map_size, gpu_address, AMDGPU_VM_PAGE_PRT, AMDGPU_VA_OP_MAP); if (r) goto error_va_map; @@ -1117,7 +1117,7 @@ static bool amdgpu_bo_sparse_commit(struct radeon_winsys *rws, struct pb_buffer_lean *buf, uint64_t offset, uint64_t size, bool commit) { - struct amdgpu_winsys *ws = amdgpu_winsys(rws); + struct amdgpu_winsys *aws = amdgpu_winsys(rws); struct amdgpu_bo_sparse *bo = get_sparse_bo(amdgpu_winsys_bo(buf)); struct amdgpu_sparse_commitment *comm; uint32_t va_page, end_va_page; @@ -1160,13 +1160,13 @@ amdgpu_bo_sparse_commit(struct radeon_winsys *rws, struct pb_buffer_lean *buf, uint32_t backing_start, backing_size; backing_size = va_page - span_va_page; - backing = sparse_backing_alloc(ws, bo, &backing_start, &backing_size); + backing = sparse_backing_alloc(aws, bo, &backing_start, &backing_size); if (!backing) { ok = false; goto out; } - r = amdgpu_bo_va_op_raw(ws->dev, backing->bo->bo_handle, + r = amdgpu_bo_va_op_raw(aws->dev, backing->bo->bo_handle, (uint64_t)backing_start * RADEON_SPARSE_PAGE_SIZE, (uint64_t)backing_size * RADEON_SPARSE_PAGE_SIZE, amdgpu_va_get_start_addr(bo->va_handle) + @@ -1176,7 +1176,7 @@ amdgpu_bo_sparse_commit(struct radeon_winsys *rws, struct pb_buffer_lean *buf, AMDGPU_VM_PAGE_EXECUTABLE, AMDGPU_VA_OP_REPLACE); if (r) { - ok = sparse_backing_free(ws, bo, backing, backing_start, backing_size); + ok = sparse_backing_free(aws, bo, backing, backing_start, backing_size); assert(ok && "sufficient memory should already be allocated"); ok = false; @@ -1193,7 +1193,7 @@ amdgpu_bo_sparse_commit(struct radeon_winsys *rws, struct pb_buffer_lean *buf, } } } else { - r = amdgpu_bo_va_op_raw(ws->dev, NULL, 0, + r = amdgpu_bo_va_op_raw(aws->dev, NULL, 0, (uint64_t)(end_va_page - va_page) * RADEON_SPARSE_PAGE_SIZE, amdgpu_va_get_start_addr(bo->va_handle) + (uint64_t)va_page * RADEON_SPARSE_PAGE_SIZE, @@ -1230,7 +1230,7 @@ amdgpu_bo_sparse_commit(struct radeon_winsys *rws, struct pb_buffer_lean *buf, span_pages++; } - if (!sparse_backing_free(ws, bo, backing, backing_start, span_pages)) { + if (!sparse_backing_free(aws, bo, backing, backing_start, span_pages)) { /* Couldn't allocate tracking data structures, so we have to leak */ fprintf(stderr, "amdgpu: leaking PRT backing memory\n"); ok = false; @@ -1303,7 +1303,7 @@ static void amdgpu_buffer_get_metadata(struct radeon_winsys *rws, struct radeon_bo_metadata *md, struct radeon_surf *surf) { - struct amdgpu_winsys *ws = amdgpu_winsys(rws); + struct amdgpu_winsys *aws = amdgpu_winsys(rws); struct amdgpu_bo_real *bo = get_real_bo(amdgpu_winsys_bo(_buf)); struct amdgpu_bo_info info = {0}; int r; @@ -1312,7 +1312,7 @@ static void amdgpu_buffer_get_metadata(struct radeon_winsys *rws, if (r) return; - ac_surface_apply_bo_metadata(&ws->info, surf, info.metadata.tiling_info, + ac_surface_apply_bo_metadata(&aws->info, surf, info.metadata.tiling_info, &md->mode); md->size_metadata = info.metadata.size_metadata; @@ -1324,11 +1324,11 @@ static void amdgpu_buffer_set_metadata(struct radeon_winsys *rws, struct radeon_bo_metadata *md, struct radeon_surf *surf) { - struct amdgpu_winsys *ws = amdgpu_winsys(rws); + struct amdgpu_winsys *aws = amdgpu_winsys(rws); struct amdgpu_bo_real *bo = get_real_bo(amdgpu_winsys_bo(_buf)); struct amdgpu_bo_metadata metadata = {0}; - ac_surface_compute_bo_metadata(&ws->info, surf, &metadata.tiling_info); + ac_surface_compute_bo_metadata(&aws->info, surf, &metadata.tiling_info); metadata.size_metadata = md->size_metadata; memcpy(metadata.umd_metadata, md->metadata, sizeof(md->metadata)); @@ -1337,7 +1337,7 @@ static void amdgpu_buffer_set_metadata(struct radeon_winsys *rws, } struct pb_buffer_lean * -amdgpu_bo_create(struct amdgpu_winsys *ws, +amdgpu_bo_create(struct amdgpu_winsys *aws, uint64_t size, unsigned alignment, enum radeon_bo_domain domain, @@ -1351,10 +1351,10 @@ amdgpu_bo_create(struct amdgpu_winsys *ws, if (flags & RADEON_FLAG_SPARSE) { assert(RADEON_SPARSE_PAGE_SIZE % alignment == 0); - return amdgpu_bo_sparse_create(ws, size, domain, flags); + return amdgpu_bo_sparse_create(aws, size, domain, flags); } - unsigned max_slab_entry_size = 1 << (ws->bo_slabs.min_order + ws->bo_slabs.num_orders - 1); + unsigned max_slab_entry_size = 1 << (aws->bo_slabs.min_order + aws->bo_slabs.num_orders - 1); int heap = radeon_get_heap_index(domain, flags); /* Sub-allocate small buffers from slabs. */ @@ -1368,11 +1368,11 @@ amdgpu_bo_create(struct amdgpu_winsys *ws, if (size < alignment && alignment <= 4 * 1024) alloc_size = alignment; - if (alignment > get_slab_entry_alignment(ws, alloc_size)) { + if (alignment > get_slab_entry_alignment(aws, alloc_size)) { /* 3/4 allocations can return too small alignment. Try again with a power of two * allocation size. */ - unsigned pot_size = get_slab_pot_entry_size(ws, alloc_size); + unsigned pot_size = get_slab_pot_entry_size(aws, alloc_size); if (alignment <= pot_size) { /* This size works but wastes some memory to fulfil the alignment. */ @@ -1382,12 +1382,12 @@ amdgpu_bo_create(struct amdgpu_winsys *ws, } } - entry = pb_slab_alloc(&ws->bo_slabs, alloc_size, heap); + entry = pb_slab_alloc(&aws->bo_slabs, alloc_size, heap); if (!entry) { /* Clean up buffer managers and try again. */ - amdgpu_clean_up_buffer_managers(ws); + amdgpu_clean_up_buffer_managers(aws); - entry = pb_slab_alloc(&ws->bo_slabs, alloc_size, heap); + entry = pb_slab_alloc(&aws->bo_slabs, alloc_size, heap); } if (!entry) return NULL; @@ -1395,13 +1395,13 @@ amdgpu_bo_create(struct amdgpu_winsys *ws, struct amdgpu_bo_slab_entry *slab_bo = container_of(entry, struct amdgpu_bo_slab_entry, entry); pipe_reference_init(&slab_bo->b.base.reference, 1); slab_bo->b.base.size = size; - slab_bo->b.unique_id = __sync_fetch_and_add(&ws->next_bo_unique_id, 1); + slab_bo->b.unique_id = __sync_fetch_and_add(&aws->next_bo_unique_id, 1); assert(alignment <= 1 << slab_bo->b.base.alignment_log2); if (domain & RADEON_DOMAIN_VRAM) - ws->slab_wasted_vram += get_slab_wasted_size(ws, slab_bo); + aws->slab_wasted_vram += get_slab_wasted_size(aws, slab_bo); else - ws->slab_wasted_gtt += get_slab_wasted_size(ws, slab_bo); + aws->slab_wasted_gtt += get_slab_wasted_size(aws, slab_bo); return &slab_bo->b.base; } @@ -1412,8 +1412,8 @@ no_slab: * like constant/uniform buffers, can benefit from better and more reuse. */ if (domain & RADEON_DOMAIN_VRAM_GTT) { - size = align64(size, ws->info.gart_page_size); - alignment = align(alignment, ws->info.gart_page_size); + size = align64(size, aws->info.gart_page_size); + alignment = align(alignment, aws->info.gart_page_size); } bool use_reusable_pool = flags & RADEON_FLAG_NO_INTERPROCESS_SHARING && @@ -1426,7 +1426,7 @@ no_slab: /* Get a buffer from the cache. */ bo = (struct amdgpu_winsys_bo*) - pb_cache_reclaim_buffer(&ws->bo_cache, size, alignment, 0, heap); + pb_cache_reclaim_buffer(&aws->bo_cache, size, alignment, 0, heap); if (bo) { /* If the buffer is amdgpu_bo_real_reusable, but we need amdgpu_bo_real_reusable_slab, * keep the allocation but make the structure bigger. @@ -1438,7 +1438,7 @@ no_slab: (struct amdgpu_winsys_bo*)REALLOC(bo, orig_size, new_size); if (!new_bo) { - amdgpu_winsys_bo_reference(ws, &bo, NULL); + amdgpu_winsys_bo_reference(aws, &bo, NULL); return NULL; } @@ -1451,12 +1451,12 @@ no_slab: } /* Create a new one. */ - bo = amdgpu_create_bo(ws, size, alignment, domain, flags, heap); + bo = amdgpu_create_bo(aws, size, alignment, domain, flags, heap); if (!bo) { /* Clean up buffer managers and try again. */ - amdgpu_clean_up_buffer_managers(ws); + amdgpu_clean_up_buffer_managers(aws); - bo = amdgpu_create_bo(ws, size, alignment, domain, flags, heap); + bo = amdgpu_create_bo(aws, size, alignment, domain, flags, heap); if (!bo) return NULL; } @@ -1481,7 +1481,7 @@ static struct pb_buffer_lean *amdgpu_bo_from_handle(struct radeon_winsys *rws, unsigned vm_alignment, bool is_prime_linear_buffer) { - struct amdgpu_winsys *ws = amdgpu_winsys(rws); + struct amdgpu_winsys *aws = amdgpu_winsys(rws); struct amdgpu_bo_real *bo = NULL; enum amdgpu_bo_handle_type type; struct amdgpu_bo_import_result result = {0}; @@ -1503,19 +1503,19 @@ static struct pb_buffer_lean *amdgpu_bo_from_handle(struct radeon_winsys *rws, return NULL; } - r = amdgpu_bo_import(ws->dev, type, whandle->handle, &result); + r = amdgpu_bo_import(aws->dev, type, whandle->handle, &result); if (r) return NULL; - simple_mtx_lock(&ws->bo_export_table_lock); - bo = util_hash_table_get(ws->bo_export_table, result.buf_handle); + simple_mtx_lock(&aws->bo_export_table_lock); + bo = util_hash_table_get(aws->bo_export_table, result.buf_handle); /* If the amdgpu_winsys_bo instance already exists, bump the reference * counter and return it. */ if (bo) { p_atomic_inc(&bo->b.base.reference.count); - simple_mtx_unlock(&ws->bo_export_table_lock); + simple_mtx_unlock(&aws->bo_export_table_lock); /* Release the buffer handle, because we don't need it anymore. * This function is returning an existing buffer, which has its own @@ -1530,9 +1530,9 @@ static struct pb_buffer_lean *amdgpu_bo_from_handle(struct radeon_winsys *rws, if (r) goto error; - r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general, + r = amdgpu_va_range_alloc(aws->dev, amdgpu_gpu_va_range_general, result.alloc_size, - amdgpu_get_optimal_alignment(ws, result.alloc_size, + amdgpu_get_optimal_alignment(aws, result.alloc_size, vm_alignment), 0, &va, &va_handle, AMDGPU_VA_RANGE_HIGH); if (r) @@ -1542,7 +1542,7 @@ static struct pb_buffer_lean *amdgpu_bo_from_handle(struct radeon_winsys *rws, if (!bo) goto error; - r = amdgpu_bo_va_op_raw(ws->dev, result.buf_handle, 0, result.alloc_size, va, + r = amdgpu_bo_va_op_raw(aws->dev, result.buf_handle, 0, result.alloc_size, va, AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_PAGE_EXECUTABLE | (is_prime_linear_buffer ? AMDGPU_VM_MTYPE_UC : 0), @@ -1571,32 +1571,32 @@ static struct pb_buffer_lean *amdgpu_bo_from_handle(struct radeon_winsys *rws, pipe_reference_init(&bo->b.base.reference, 1); bo->b.base.placement = initial; bo->b.base.alignment_log2 = util_logbase2(info.phys_alignment ? - info.phys_alignment : ws->info.gart_page_size); + info.phys_alignment : aws->info.gart_page_size); bo->b.base.usage = flags; bo->b.base.size = result.alloc_size; bo->b.type = AMDGPU_BO_REAL; - bo->b.unique_id = __sync_fetch_and_add(&ws->next_bo_unique_id, 1); + bo->b.unique_id = __sync_fetch_and_add(&aws->next_bo_unique_id, 1); simple_mtx_init(&bo->map_lock, mtx_plain); bo->bo_handle = result.buf_handle; bo->va_handle = va_handle; bo->is_shared = true; if (bo->b.base.placement & RADEON_DOMAIN_VRAM) - ws->allocated_vram += align64(bo->b.base.size, ws->info.gart_page_size); + aws->allocated_vram += align64(bo->b.base.size, aws->info.gart_page_size); else if (bo->b.base.placement & RADEON_DOMAIN_GTT) - ws->allocated_gtt += align64(bo->b.base.size, ws->info.gart_page_size); + aws->allocated_gtt += align64(bo->b.base.size, aws->info.gart_page_size); amdgpu_bo_export(bo->bo_handle, amdgpu_bo_handle_type_kms, &bo->kms_handle); - amdgpu_add_buffer_to_global_list(ws, bo); + amdgpu_add_buffer_to_global_list(aws, bo); - _mesa_hash_table_insert(ws->bo_export_table, bo->bo_handle, bo); - simple_mtx_unlock(&ws->bo_export_table_lock); + _mesa_hash_table_insert(aws->bo_export_table, bo->bo_handle, bo); + simple_mtx_unlock(&aws->bo_export_table_lock); return &bo->b.base; error: - simple_mtx_unlock(&ws->bo_export_table_lock); + simple_mtx_unlock(&aws->bo_export_table_lock); if (bo) FREE(bo); if (va_handle) @@ -1610,7 +1610,7 @@ static bool amdgpu_bo_get_handle(struct radeon_winsys *rws, struct winsys_handle *whandle) { struct amdgpu_screen_winsys *sws = amdgpu_screen_winsys(rws); - struct amdgpu_winsys *ws = amdgpu_winsys(rws); + struct amdgpu_winsys *aws = amdgpu_winsys(rws); enum amdgpu_bo_handle_type type; struct hash_entry *entry; int r; @@ -1629,7 +1629,7 @@ static bool amdgpu_bo_get_handle(struct radeon_winsys *rws, type = amdgpu_bo_handle_type_gem_flink_name; break; case WINSYS_HANDLE_TYPE_KMS: - if (sws->fd == ws->fd) { + if (sws->fd == aws->fd) { whandle->handle = bo->kms_handle; if (bo->is_shared) @@ -1638,9 +1638,9 @@ static bool amdgpu_bo_get_handle(struct radeon_winsys *rws, goto hash_table_set; } - simple_mtx_lock(&ws->sws_list_lock); + simple_mtx_lock(&aws->sws_list_lock); entry = _mesa_hash_table_search(sws->kms_handles, bo); - simple_mtx_unlock(&ws->sws_list_lock); + simple_mtx_unlock(&aws->sws_list_lock); if (entry) { whandle->handle = (uintptr_t)entry->data; return true; @@ -1675,17 +1675,17 @@ static bool amdgpu_bo_get_handle(struct radeon_winsys *rws, if (r) return false; - simple_mtx_lock(&ws->sws_list_lock); + simple_mtx_lock(&aws->sws_list_lock); _mesa_hash_table_insert_pre_hashed(sws->kms_handles, bo->kms_handle, bo, (void*)(uintptr_t)whandle->handle); - simple_mtx_unlock(&ws->sws_list_lock); + simple_mtx_unlock(&aws->sws_list_lock); } hash_table_set: - simple_mtx_lock(&ws->bo_export_table_lock); - _mesa_hash_table_insert(ws->bo_export_table, bo->bo_handle, bo); - simple_mtx_unlock(&ws->bo_export_table_lock); + simple_mtx_lock(&aws->bo_export_table_lock); + _mesa_hash_table_insert(aws->bo_export_table, bo->bo_handle, bo); + simple_mtx_unlock(&aws->bo_export_table_lock); bo->is_shared = true; return true; @@ -1695,26 +1695,26 @@ static struct pb_buffer_lean *amdgpu_bo_from_ptr(struct radeon_winsys *rws, void *pointer, uint64_t size, enum radeon_bo_flag flags) { - struct amdgpu_winsys *ws = amdgpu_winsys(rws); + struct amdgpu_winsys *aws = amdgpu_winsys(rws); amdgpu_bo_handle buf_handle; struct amdgpu_bo_real *bo; uint64_t va; amdgpu_va_handle va_handle; /* Avoid failure when the size is not page aligned */ - uint64_t aligned_size = align64(size, ws->info.gart_page_size); + uint64_t aligned_size = align64(size, aws->info.gart_page_size); bo = CALLOC_STRUCT(amdgpu_bo_real); if (!bo) return NULL; - if (amdgpu_create_bo_from_user_mem(ws->dev, pointer, + if (amdgpu_create_bo_from_user_mem(aws->dev, pointer, aligned_size, &buf_handle)) goto error; - if (amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general, + if (amdgpu_va_range_alloc(aws->dev, amdgpu_gpu_va_range_general, aligned_size, - amdgpu_get_optimal_alignment(ws, aligned_size, - ws->info.gart_page_size), + amdgpu_get_optimal_alignment(aws, aligned_size, + aws->info.gart_page_size), 0, &va, &va_handle, AMDGPU_VA_RANGE_HIGH)) goto error_va_alloc; @@ -1728,15 +1728,15 @@ static struct pb_buffer_lean *amdgpu_bo_from_ptr(struct radeon_winsys *rws, bo->b.base.alignment_log2 = 0; bo->b.base.size = size; bo->b.type = AMDGPU_BO_REAL; - bo->b.unique_id = __sync_fetch_and_add(&ws->next_bo_unique_id, 1); + bo->b.unique_id = __sync_fetch_and_add(&aws->next_bo_unique_id, 1); simple_mtx_init(&bo->map_lock, mtx_plain); bo->bo_handle = buf_handle; bo->cpu_ptr = pointer; bo->va_handle = va_handle; - ws->allocated_gtt += aligned_size; + aws->allocated_gtt += aligned_size; - amdgpu_add_buffer_to_global_list(ws, bo); + amdgpu_add_buffer_to_global_list(aws, bo); amdgpu_bo_export(bo->bo_handle, amdgpu_bo_handle_type_kms, &bo->kms_handle); diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h index d81d6612f2e..049efd0e3f0 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h @@ -203,7 +203,7 @@ static struct amdgpu_bo_real_reusable_slab *get_real_bo_reusable_slab(struct amd * to set the fence to NULL in the ring, which is why we return a pointer to a pointer. */ static inline struct pipe_fence_handle ** -get_fence_from_ring(struct amdgpu_winsys *ws, struct amdgpu_seq_no_fences *fences, +get_fence_from_ring(struct amdgpu_winsys *aws, struct amdgpu_seq_no_fences *fences, unsigned queue_index) { /* The caller should check if the BO has a fence. */ @@ -211,12 +211,12 @@ get_fence_from_ring(struct amdgpu_winsys *ws, struct amdgpu_seq_no_fences *fence assert(fences->valid_fence_mask & BITFIELD_BIT(queue_index)); uint_seq_no buffer_seq_no = fences->seq_no[queue_index]; - uint_seq_no latest_seq_no = ws->queues[queue_index].latest_seq_no; + uint_seq_no latest_seq_no = aws->queues[queue_index].latest_seq_no; bool fence_present = latest_seq_no - buffer_seq_no < AMDGPU_FENCE_RING_SIZE; if (fence_present) { struct pipe_fence_handle **fence = - &ws->queues[queue_index].fences[buffer_seq_no % AMDGPU_FENCE_RING_SIZE]; + &aws->queues[queue_index].fences[buffer_seq_no % AMDGPU_FENCE_RING_SIZE]; if (*fence) return fence; @@ -229,10 +229,10 @@ get_fence_from_ring(struct amdgpu_winsys *ws, struct amdgpu_seq_no_fences *fence return NULL; } -static inline uint_seq_no pick_latest_seq_no(struct amdgpu_winsys *ws, unsigned queue_index, +static inline uint_seq_no pick_latest_seq_no(struct amdgpu_winsys *aws, unsigned queue_index, uint_seq_no n1, uint_seq_no n2) { - uint_seq_no latest = ws->queues[queue_index].latest_seq_no; + uint_seq_no latest = aws->queues[queue_index].latest_seq_no; /* Since sequence numbers can wrap around, we need to pick the later number that's logically * before "latest". The trick is to subtract "latest + 1" to underflow integer such @@ -244,11 +244,11 @@ static inline uint_seq_no pick_latest_seq_no(struct amdgpu_winsys *ws, unsigned return s1 >= s2 ? n1 : n2; } -static inline void add_seq_no_to_list(struct amdgpu_winsys *ws, struct amdgpu_seq_no_fences *fences, +static inline void add_seq_no_to_list(struct amdgpu_winsys *aws, struct amdgpu_seq_no_fences *fences, unsigned queue_index, uint_seq_no seq_no) { if (fences->valid_fence_mask & BITFIELD_BIT(queue_index)) { - fences->seq_no[queue_index] = pick_latest_seq_no(ws, queue_index, seq_no, + fences->seq_no[queue_index] = pick_latest_seq_no(aws, queue_index, seq_no, fences->seq_no[queue_index]); } else { fences->seq_no[queue_index] = seq_no; @@ -256,13 +256,13 @@ static inline void add_seq_no_to_list(struct amdgpu_winsys *ws, struct amdgpu_se } } -bool amdgpu_bo_can_reclaim(struct amdgpu_winsys *ws, struct pb_buffer_lean *_buf); -struct pb_buffer_lean *amdgpu_bo_create(struct amdgpu_winsys *ws, +bool amdgpu_bo_can_reclaim(struct amdgpu_winsys *aws, struct pb_buffer_lean *_buf); +struct pb_buffer_lean *amdgpu_bo_create(struct amdgpu_winsys *aws, uint64_t size, unsigned alignment, enum radeon_bo_domain domain, enum radeon_bo_flag flags); -void amdgpu_bo_destroy(struct amdgpu_winsys *ws, struct pb_buffer_lean *_buf); +void amdgpu_bo_destroy(struct amdgpu_winsys *aws, struct pb_buffer_lean *_buf); void *amdgpu_bo_map(struct radeon_winsys *rws, struct pb_buffer_lean *buf, struct radeon_cmdbuf *rcs, @@ -273,7 +273,7 @@ void amdgpu_bo_init_functions(struct amdgpu_screen_winsys *sws); bool amdgpu_bo_can_reclaim_slab(void *priv, struct pb_slab_entry *entry); struct pb_slab *amdgpu_bo_slab_alloc(void *priv, unsigned heap, unsigned entry_size, unsigned group_index); -void amdgpu_bo_slab_free(struct amdgpu_winsys *ws, struct pb_slab *slab); +void amdgpu_bo_slab_free(struct amdgpu_winsys *aws, struct pb_slab *slab); uint64_t amdgpu_bo_get_va(struct pb_buffer_lean *buf); static inline struct amdgpu_winsys_bo * @@ -283,10 +283,10 @@ amdgpu_winsys_bo(struct pb_buffer_lean *bo) } static inline void -amdgpu_winsys_bo_reference(struct amdgpu_winsys *ws, struct amdgpu_winsys_bo **dst, +amdgpu_winsys_bo_reference(struct amdgpu_winsys *aws, struct amdgpu_winsys_bo **dst, struct amdgpu_winsys_bo *src) { - radeon_bo_reference(&ws->dummy_sws.base, + radeon_bo_reference(&aws->dummy_sws.base, (struct pb_buffer_lean**)dst, (struct pb_buffer_lean*)src); } @@ -299,9 +299,9 @@ amdgpu_winsys_bo_set_reference(struct amdgpu_winsys_bo **dst, struct amdgpu_wins /* Unreference dst, but don't assign anything. */ static inline void -amdgpu_winsys_bo_drop_reference(struct amdgpu_winsys *ws, struct amdgpu_winsys_bo *dst) +amdgpu_winsys_bo_drop_reference(struct amdgpu_winsys *aws, struct amdgpu_winsys_bo *dst) { - radeon_bo_drop_reference(&ws->dummy_sws.base, &dst->base); + radeon_bo_drop_reference(&aws->dummy_sws.base, &dst->base); } #ifdef __cplusplus diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.cpp b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.cpp index 627ee7e6769..fb8d01c005f 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.cpp +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.cpp @@ -27,7 +27,7 @@ void amdgpu_fence_destroy(struct amdgpu_fence *fence) { - amdgpu_cs_destroy_syncobj(fence->ws->dev, fence->syncobj); + amdgpu_cs_destroy_syncobj(fence->aws->dev, fence->syncobj); if (fence->ctx) amdgpu_ctx_reference(&fence->ctx, NULL); @@ -43,11 +43,11 @@ amdgpu_fence_create(struct amdgpu_cs *cs) struct amdgpu_ctx *ctx = cs->ctx; fence->reference.count = 1; - fence->ws = ctx->ws; + fence->aws = ctx->aws; amdgpu_ctx_reference(&fence->ctx, ctx); fence->ctx = ctx; fence->ip_type = cs->ip_type; - if (amdgpu_cs_create_syncobj2(ctx->ws->dev, 0, &fence->syncobj)) { + if (amdgpu_cs_create_syncobj2(ctx->aws->dev, 0, &fence->syncobj)) { free(fence); return NULL; } @@ -61,7 +61,7 @@ amdgpu_fence_create(struct amdgpu_cs *cs) static struct pipe_fence_handle * amdgpu_fence_import_syncobj(struct radeon_winsys *rws, int fd) { - struct amdgpu_winsys *ws = amdgpu_winsys(rws); + struct amdgpu_winsys *aws = amdgpu_winsys(rws); struct amdgpu_fence *fence = CALLOC_STRUCT(amdgpu_fence); int r; @@ -69,10 +69,10 @@ amdgpu_fence_import_syncobj(struct radeon_winsys *rws, int fd) return NULL; pipe_reference_init(&fence->reference, 1); - fence->ws = ws; + fence->aws = aws; fence->ip_type = 0xffffffff; - r = amdgpu_cs_import_syncobj(ws->dev, fd, &fence->syncobj); + r = amdgpu_cs_import_syncobj(aws->dev, fd, &fence->syncobj); if (r) { FREE(fence); return NULL; @@ -87,26 +87,26 @@ amdgpu_fence_import_syncobj(struct radeon_winsys *rws, int fd) static struct pipe_fence_handle * amdgpu_fence_import_sync_file(struct radeon_winsys *rws, int fd) { - struct amdgpu_winsys *ws = amdgpu_winsys(rws); + struct amdgpu_winsys *aws = amdgpu_winsys(rws); struct amdgpu_fence *fence = CALLOC_STRUCT(amdgpu_fence); if (!fence) return NULL; pipe_reference_init(&fence->reference, 1); - fence->ws = ws; + fence->aws = aws; /* fence->ctx == NULL means that the fence is syncobj-based. */ /* Convert sync_file into syncobj. */ - int r = amdgpu_cs_create_syncobj(ws->dev, &fence->syncobj); + int r = amdgpu_cs_create_syncobj(aws->dev, &fence->syncobj); if (r) { FREE(fence); return NULL; } - r = amdgpu_cs_syncobj_import_sync_file(ws->dev, fence->syncobj, fd); + r = amdgpu_cs_syncobj_import_sync_file(aws->dev, fence->syncobj, fd); if (r) { - amdgpu_cs_destroy_syncobj(ws->dev, fence->syncobj); + amdgpu_cs_destroy_syncobj(aws->dev, fence->syncobj); FREE(fence); return NULL; } @@ -120,35 +120,35 @@ amdgpu_fence_import_sync_file(struct radeon_winsys *rws, int fd) static int amdgpu_fence_export_sync_file(struct radeon_winsys *rws, struct pipe_fence_handle *pfence) { - struct amdgpu_winsys *ws = amdgpu_winsys(rws); + struct amdgpu_winsys *aws = amdgpu_winsys(rws); struct amdgpu_fence *fence = (struct amdgpu_fence*)pfence; int fd, r; util_queue_fence_wait(&fence->submitted); /* Convert syncobj into sync_file. */ - r = amdgpu_cs_syncobj_export_sync_file(ws->dev, fence->syncobj, &fd); + r = amdgpu_cs_syncobj_export_sync_file(aws->dev, fence->syncobj, &fd); return r ? -1 : fd; } static int amdgpu_export_signalled_sync_file(struct radeon_winsys *rws) { - struct amdgpu_winsys *ws = amdgpu_winsys(rws); + struct amdgpu_winsys *aws = amdgpu_winsys(rws); uint32_t syncobj; int fd = -1; - int r = amdgpu_cs_create_syncobj2(ws->dev, DRM_SYNCOBJ_CREATE_SIGNALED, + int r = amdgpu_cs_create_syncobj2(aws->dev, DRM_SYNCOBJ_CREATE_SIGNALED, &syncobj); if (r) { return -1; } - r = amdgpu_cs_syncobj_export_sync_file(ws->dev, syncobj, &fd); + r = amdgpu_cs_syncobj_export_sync_file(aws->dev, syncobj, &fd); if (r) { fd = -1; } - amdgpu_cs_destroy_syncobj(ws->dev, syncobj); + amdgpu_cs_destroy_syncobj(aws->dev, syncobj); return fd; } @@ -207,7 +207,7 @@ bool amdgpu_fence_wait(struct pipe_fence_handle *fence, uint64_t timeout, if ((uint64_t)abs_timeout == OS_TIMEOUT_INFINITE) abs_timeout = INT64_MAX; - if (amdgpu_cs_syncobj_wait(afence->ws->dev, &afence->syncobj, 1, + if (amdgpu_cs_syncobj_wait(afence->aws->dev, &afence->syncobj, 1, abs_timeout, 0, NULL)) return false; @@ -277,21 +277,21 @@ static struct radeon_winsys_ctx *amdgpu_ctx_create(struct radeon_winsys *rws, if (!ctx) return NULL; - ctx->ws = amdgpu_winsys(rws); + ctx->aws = amdgpu_winsys(rws); ctx->reference.count = 1; ctx->allow_context_lost = allow_context_lost; - r = amdgpu_cs_ctx_create2(ctx->ws->dev, amdgpu_priority, &ctx->ctx); + r = amdgpu_cs_ctx_create2(ctx->aws->dev, amdgpu_priority, &ctx->ctx); if (r) { fprintf(stderr, "amdgpu: amdgpu_cs_ctx_create2 failed. (%i)\n", r); goto error_create; } - alloc_buffer.alloc_size = ctx->ws->info.gart_page_size; - alloc_buffer.phys_alignment = ctx->ws->info.gart_page_size; + alloc_buffer.alloc_size = ctx->aws->info.gart_page_size; + alloc_buffer.phys_alignment = ctx->aws->info.gart_page_size; alloc_buffer.preferred_heap = AMDGPU_GEM_DOMAIN_GTT; - r = amdgpu_bo_alloc(ctx->ws->dev, &alloc_buffer, &buf_handle); + r = amdgpu_bo_alloc(ctx->aws->dev, &alloc_buffer, &buf_handle); if (r) { fprintf(stderr, "amdgpu: amdgpu_bo_alloc failed. (%i)\n", r); goto error_user_fence_alloc; @@ -324,17 +324,17 @@ static void amdgpu_ctx_destroy(struct radeon_winsys_ctx *rwctx) amdgpu_ctx_reference(&ctx, NULL); } -static void amdgpu_pad_gfx_compute_ib(struct amdgpu_winsys *ws, enum amd_ip_type ip_type, +static void amdgpu_pad_gfx_compute_ib(struct amdgpu_winsys *aws, enum amd_ip_type ip_type, uint32_t *ib, uint32_t *num_dw, unsigned leave_dw_space) { - unsigned pad_dw_mask = ws->info.ip[ip_type].ib_pad_dw_mask; + unsigned pad_dw_mask = aws->info.ip[ip_type].ib_pad_dw_mask; unsigned unaligned_dw = (*num_dw + leave_dw_space) & pad_dw_mask; if (unaligned_dw) { int remaining = pad_dw_mask + 1 - unaligned_dw; /* Only pad by 1 dword with the type-2 NOP if necessary. */ - if (remaining == 1 && ws->info.gfx_ib_pad_with_type2) { + if (remaining == 1 && aws->info.gfx_ib_pad_with_type2) { ib[(*num_dw)++] = PKT2_NOP_PAD; } else { /* Pad with a single NOP packet to minimize CP overhead because NOP is a variable-sized @@ -369,24 +369,24 @@ static int amdgpu_submit_gfx_nop(struct amdgpu_ctx *ctx) * that the reset is not complete. */ amdgpu_context_handle temp_ctx; - r = amdgpu_cs_ctx_create2(ctx->ws->dev, AMDGPU_CTX_PRIORITY_NORMAL, &temp_ctx); + r = amdgpu_cs_ctx_create2(ctx->aws->dev, AMDGPU_CTX_PRIORITY_NORMAL, &temp_ctx); if (r) return r; request.preferred_heap = AMDGPU_GEM_DOMAIN_VRAM; request.alloc_size = 4096; request.phys_alignment = 4096; - r = amdgpu_bo_alloc(ctx->ws->dev, &request, &buf_handle); + r = amdgpu_bo_alloc(ctx->aws->dev, &request, &buf_handle); if (r) goto destroy_ctx; - r = amdgpu_va_range_alloc(ctx->ws->dev, amdgpu_gpu_va_range_general, + r = amdgpu_va_range_alloc(ctx->aws->dev, amdgpu_gpu_va_range_general, request.alloc_size, request.phys_alignment, 0, &va, &va_handle, AMDGPU_VA_RANGE_32_BIT | AMDGPU_VA_RANGE_HIGH); if (r) goto destroy_bo; - r = amdgpu_bo_va_op_raw(ctx->ws->dev, buf_handle, 0, request.alloc_size, va, + r = amdgpu_bo_va_op_raw(ctx->aws->dev, buf_handle, 0, request.alloc_size, va, AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_PAGE_EXECUTABLE, AMDGPU_VA_OP_MAP); if (r) @@ -396,7 +396,7 @@ static int amdgpu_submit_gfx_nop(struct amdgpu_ctx *ctx) if (r) goto destroy_bo; - noop_dw_size = ctx->ws->info.ip[AMD_IP_GFX].ib_pad_dw_mask + 1; + noop_dw_size = ctx->aws->info.ip[AMD_IP_GFX].ib_pad_dw_mask + 1; ((uint32_t*)cpu)[0] = PKT3(PKT3_NOP, noop_dw_size - 2, 0); amdgpu_bo_cpu_unmap(buf_handle); @@ -421,7 +421,7 @@ static int amdgpu_submit_gfx_nop(struct amdgpu_ctx *ctx) chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4; chunks[1].chunk_data = (uintptr_t)&ib_in; - r = amdgpu_cs_submit_raw2(ctx->ws->dev, temp_ctx, 0, 2, chunks, &seq_no); + r = amdgpu_cs_submit_raw2(ctx->aws->dev, temp_ctx, 0, 2, chunks, &seq_no); destroy_bo: if (va_handle) @@ -506,7 +506,7 @@ amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx *rwctx, bool full_reset_o if (!(flags & AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS)) *reset_completed = true; - if (ctx->ws->info.drm_minor < 54 && ctx->ws->info.has_graphics) + if (ctx->aws->info.drm_minor < 54 && ctx->aws->info.has_graphics) *reset_completed = amdgpu_submit_gfx_nop(ctx) == 0; } } @@ -657,7 +657,7 @@ static unsigned amdgpu_cs_add_buffer(struct radeon_cmdbuf *rcs, return 0; } -static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *ws, +static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *aws, struct amdgpu_ib *main_ib, struct amdgpu_cs *cs) { @@ -701,20 +701,20 @@ static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *ws, flags |= RADEON_FLAG_32BIT; } - pb = amdgpu_bo_create(ws, buffer_size, - ws->info.gart_page_size, + pb = amdgpu_bo_create(aws, buffer_size, + aws->info.gart_page_size, domain, (radeon_bo_flag)flags); if (!pb) return false; - mapped = (uint8_t*)amdgpu_bo_map(&ws->dummy_sws.base, pb, NULL, PIPE_MAP_WRITE); + mapped = (uint8_t*)amdgpu_bo_map(&aws->dummy_sws.base, pb, NULL, PIPE_MAP_WRITE); if (!mapped) { - radeon_bo_reference(&ws->dummy_sws.base, &pb, NULL); + radeon_bo_reference(&aws->dummy_sws.base, &pb, NULL); return false; } - radeon_bo_reference(&ws->dummy_sws.base, &main_ib->big_buffer, pb); - radeon_bo_reference(&ws->dummy_sws.base, &pb, NULL); + radeon_bo_reference(&aws->dummy_sws.base, &main_ib->big_buffer, pb); + radeon_bo_reference(&aws->dummy_sws.base, &pb, NULL); main_ib->gpu_address = amdgpu_bo_get_va(main_ib->big_buffer); main_ib->big_buffer_cpu_ptr = mapped; @@ -723,7 +723,7 @@ static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *ws, return true; } -static bool amdgpu_get_new_ib(struct amdgpu_winsys *ws, +static bool amdgpu_get_new_ib(struct amdgpu_winsys *aws, struct radeon_cmdbuf *rcs, struct amdgpu_ib *main_ib, struct amdgpu_cs *cs) @@ -755,7 +755,7 @@ static bool amdgpu_get_new_ib(struct amdgpu_winsys *ws, /* Allocate a new buffer for IBs if the current buffer is all used. */ if (!main_ib->big_buffer || main_ib->used_ib_space + ib_size > main_ib->big_buffer->size) { - if (!amdgpu_ib_new_buffer(ws, main_ib, cs)) + if (!amdgpu_ib_new_buffer(aws, main_ib, cs)) return false; } @@ -790,16 +790,16 @@ static void amdgpu_set_ib_size(struct radeon_cmdbuf *rcs, struct amdgpu_ib *ib) } } -static void amdgpu_ib_finalize(struct amdgpu_winsys *ws, struct radeon_cmdbuf *rcs, +static void amdgpu_ib_finalize(struct amdgpu_winsys *aws, struct radeon_cmdbuf *rcs, struct amdgpu_ib *ib, enum amd_ip_type ip_type) { amdgpu_set_ib_size(rcs, ib); ib->used_ib_space += rcs->current.cdw * 4; - ib->used_ib_space = align(ib->used_ib_space, ws->info.ip[ip_type].ib_alignment); + ib->used_ib_space = align(ib->used_ib_space, aws->info.ip[ip_type].ib_alignment); ib->max_ib_bytes = MAX2(ib->max_ib_bytes, (rcs->prev_dw + rcs->current.cdw) * 4); } -static bool amdgpu_init_cs_context(struct amdgpu_winsys *ws, +static bool amdgpu_init_cs_context(struct amdgpu_winsys *aws, struct amdgpu_cs_context *cs, enum amd_ip_type ip_type) { @@ -831,20 +831,20 @@ static void cleanup_fence_list(struct amdgpu_fence_list *fences) fences->num = 0; } -static void amdgpu_cs_context_cleanup_buffers(struct amdgpu_winsys *ws, struct amdgpu_cs_context *cs) +static void amdgpu_cs_context_cleanup_buffers(struct amdgpu_winsys *aws, struct amdgpu_cs_context *cs) { for (unsigned i = 0; i < ARRAY_SIZE(cs->buffer_lists); i++) { struct amdgpu_cs_buffer *buffers = cs->buffer_lists[i].buffers; unsigned num_buffers = cs->buffer_lists[i].num_buffers; for (unsigned j = 0; j < num_buffers; j++) - amdgpu_winsys_bo_drop_reference(ws, buffers[j].bo); + amdgpu_winsys_bo_drop_reference(aws, buffers[j].bo); cs->buffer_lists[i].num_buffers = 0; } } -static void amdgpu_cs_context_cleanup(struct amdgpu_winsys *ws, struct amdgpu_cs_context *cs) +static void amdgpu_cs_context_cleanup(struct amdgpu_winsys *aws, struct amdgpu_cs_context *cs) { cs->seq_no_dependencies.valid_fence_mask = 0; cleanup_fence_list(&cs->syncobj_dependencies); @@ -853,10 +853,10 @@ static void amdgpu_cs_context_cleanup(struct amdgpu_winsys *ws, struct amdgpu_cs cs->last_added_bo = NULL; } -static void amdgpu_destroy_cs_context(struct amdgpu_winsys *ws, struct amdgpu_cs_context *cs) +static void amdgpu_destroy_cs_context(struct amdgpu_winsys *aws, struct amdgpu_cs_context *cs) { - amdgpu_cs_context_cleanup_buffers(ws, cs); - amdgpu_cs_context_cleanup(ws, cs); + amdgpu_cs_context_cleanup_buffers(aws, cs); + amdgpu_cs_context_cleanup(aws, cs); for (unsigned i = 0; i < ARRAY_SIZE(cs->buffer_lists); i++) FREE(cs->buffer_lists[i].buffers); FREE(cs->syncobj_dependencies.list); @@ -896,18 +896,18 @@ amdgpu_cs_create(struct radeon_cmdbuf *rcs, util_queue_fence_init(&cs->flush_completed); - cs->ws = ctx->ws; + cs->aws = ctx->aws; cs->ctx = ctx; cs->flush_cs = flush; cs->flush_data = flush_ctx; cs->ip_type = ip_type; - cs->noop = ctx->ws->noop_cs; - cs->has_chaining = ctx->ws->info.gfx_level >= GFX7 && + cs->noop = ctx->aws->noop_cs; + cs->has_chaining = ctx->aws->info.gfx_level >= GFX7 && (ip_type == AMD_IP_GFX || ip_type == AMD_IP_COMPUTE); /* Compute the queue index by counting the IPs that have queues. */ - assert(ip_type < ARRAY_SIZE(ctx->ws->info.ip)); - assert(ctx->ws->info.ip[ip_type].num_queues); + assert(ip_type < ARRAY_SIZE(ctx->aws->info.ip)); + assert(ctx->aws->info.ip[ip_type].num_queues); if (ip_uses_alt_fence(ip_type)) { cs->queue_index = INT_MAX; @@ -915,8 +915,8 @@ amdgpu_cs_create(struct radeon_cmdbuf *rcs, } else { cs->queue_index = 0; - for (unsigned i = 0; i < ARRAY_SIZE(ctx->ws->info.ip); i++) { - if (!ctx->ws->info.ip[i].num_queues || ip_uses_alt_fence((amd_ip_type)i)) + for (unsigned i = 0; i < ARRAY_SIZE(ctx->aws->info.ip); i++) { + if (!ctx->aws->info.ip[i].num_queues || ip_uses_alt_fence((amd_ip_type)i)) continue; if (i == ip_type) @@ -933,13 +933,13 @@ amdgpu_cs_create(struct radeon_cmdbuf *rcs, amdgpu_cs_chunk_fence_info_to_data(&fence_info, (struct drm_amdgpu_cs_chunk_data*)&cs->fence_chunk); - if (!amdgpu_init_cs_context(ctx->ws, &cs->csc1, ip_type)) { + if (!amdgpu_init_cs_context(ctx->aws, &cs->csc1, ip_type)) { FREE(cs); return false; } - if (!amdgpu_init_cs_context(ctx->ws, &cs->csc2, ip_type)) { - amdgpu_destroy_cs_context(ctx->ws, &cs->csc1); + if (!amdgpu_init_cs_context(ctx->aws, &cs->csc2, ip_type)) { + amdgpu_destroy_cs_context(ctx->aws, &cs->csc1); FREE(cs); return false; } @@ -954,20 +954,20 @@ amdgpu_cs_create(struct radeon_cmdbuf *rcs, cs->csc1.buffer_indices_hashlist = cs->buffer_indices_hashlist; cs->csc2.buffer_indices_hashlist = cs->buffer_indices_hashlist; - cs->csc1.ws = ctx->ws; - cs->csc2.ws = ctx->ws; + cs->csc1.aws = ctx->aws; + cs->csc2.aws = ctx->aws; rcs->priv = cs; - if (!amdgpu_get_new_ib(ctx->ws, rcs, &cs->main_ib, cs)) { - amdgpu_destroy_cs_context(ctx->ws, &cs->csc2); - amdgpu_destroy_cs_context(ctx->ws, &cs->csc1); + if (!amdgpu_get_new_ib(ctx->aws, rcs, &cs->main_ib, cs)) { + amdgpu_destroy_cs_context(ctx->aws, &cs->csc2); + amdgpu_destroy_cs_context(ctx->aws, &cs->csc1); FREE(cs); rcs->priv = NULL; return false; } - p_atomic_inc(&ctx->ws->num_cs); + p_atomic_inc(&ctx->aws->num_cs); return true; } @@ -976,14 +976,14 @@ amdgpu_cs_setup_preemption(struct radeon_cmdbuf *rcs, const uint32_t *preamble_i unsigned preamble_num_dw) { struct amdgpu_cs *cs = amdgpu_cs(rcs); - struct amdgpu_winsys *ws = cs->ws; + struct amdgpu_winsys *aws = cs->aws; struct amdgpu_cs_context *csc[2] = {&cs->csc1, &cs->csc2}; - unsigned size = align(preamble_num_dw * 4, ws->info.ip[AMD_IP_GFX].ib_alignment); + unsigned size = align(preamble_num_dw * 4, aws->info.ip[AMD_IP_GFX].ib_alignment); struct pb_buffer_lean *preamble_bo; uint32_t *map; /* Create the preamble IB buffer. */ - preamble_bo = amdgpu_bo_create(ws, size, ws->info.ip[AMD_IP_GFX].ib_alignment, + preamble_bo = amdgpu_bo_create(aws, size, aws->info.ip[AMD_IP_GFX].ib_alignment, RADEON_DOMAIN_VRAM, (radeon_bo_flag) (RADEON_FLAG_NO_INTERPROCESS_SHARING | @@ -992,10 +992,10 @@ amdgpu_cs_setup_preemption(struct radeon_cmdbuf *rcs, const uint32_t *preamble_i if (!preamble_bo) return false; - map = (uint32_t*)amdgpu_bo_map(&ws->dummy_sws.base, preamble_bo, NULL, + map = (uint32_t*)amdgpu_bo_map(&aws->dummy_sws.base, preamble_bo, NULL, (pipe_map_flags)(PIPE_MAP_WRITE | RADEON_MAP_TEMPORARY)); if (!map) { - radeon_bo_reference(&ws->dummy_sws.base, &preamble_bo, NULL); + radeon_bo_reference(&aws->dummy_sws.base, &preamble_bo, NULL); return false; } @@ -1003,8 +1003,8 @@ amdgpu_cs_setup_preemption(struct radeon_cmdbuf *rcs, const uint32_t *preamble_i memcpy(map, preamble_ib, preamble_num_dw * 4); /* Pad the IB. */ - amdgpu_pad_gfx_compute_ib(ws, cs->ip_type, map, &preamble_num_dw, 0); - amdgpu_bo_unmap(&ws->dummy_sws.base, preamble_bo); + amdgpu_pad_gfx_compute_ib(aws, cs->ip_type, map, &preamble_num_dw, 0); + amdgpu_bo_unmap(&aws->dummy_sws.base, preamble_bo); for (unsigned i = 0; i < 2; i++) { csc[i]->chunk_ib[IB_PREAMBLE].va_start = amdgpu_bo_get_va(preamble_bo); @@ -1066,7 +1066,7 @@ static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw) rcs->max_prev = new_max_prev; } - if (!amdgpu_ib_new_buffer(cs->ws, main_ib, cs)) + if (!amdgpu_ib_new_buffer(cs->aws, main_ib, cs)) return false; assert(main_ib->used_ib_space == 0); @@ -1076,14 +1076,14 @@ static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw) rcs->current.max_dw += cs_epilog_dw; /* Pad with NOPs but leave 4 dwords for INDIRECT_BUFFER. */ - amdgpu_pad_gfx_compute_ib(cs->ws, cs->ip_type, rcs->current.buf, &rcs->current.cdw, 4); + amdgpu_pad_gfx_compute_ib(cs->aws, cs->ip_type, rcs->current.buf, &rcs->current.cdw, 4); radeon_emit(rcs, PKT3(PKT3_INDIRECT_BUFFER, 2, 0)); radeon_emit(rcs, va); radeon_emit(rcs, va >> 32); uint32_t *new_ptr_ib_size = &rcs->current.buf[rcs->current.cdw++]; - assert((rcs->current.cdw & cs->ws->info.ip[cs->ip_type].ib_pad_dw_mask) == 0); + assert((rcs->current.cdw & cs->aws->info.ip[cs->ip_type].ib_pad_dw_mask) == 0); assert(rcs->current.cdw <= rcs->current.max_dw); amdgpu_set_ib_size(rcs, main_ib); @@ -1180,7 +1180,7 @@ static void amdgpu_cs_add_fence_dependency(struct radeon_cmdbuf *rcs, if (!fence->imported) { /* Ignore idle fences. This will only check the user fence in memory. */ if (!amdgpu_fence_wait((struct pipe_fence_handle *)fence, 0, false)) { - add_seq_no_to_list(acs->ws, &cs->seq_no_dependencies, fence->queue_index, + add_seq_no_to_list(acs->aws, &cs->seq_no_dependencies, fence->queue_index, fence->queue_seq_no); } } @@ -1237,7 +1237,7 @@ template static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index) { struct amdgpu_cs *acs = (struct amdgpu_cs*)job; - struct amdgpu_winsys *ws = acs->ws; + struct amdgpu_winsys *aws = acs->aws; struct amdgpu_cs_context *cs = acs->cst; int r; uint64_t seq_no = 0; @@ -1245,14 +1245,14 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index) assert(QUEUE_USES_ALT_FENCE == acs->uses_alt_fence); - simple_mtx_lock(&ws->bo_fence_lock); + simple_mtx_lock(&aws->bo_fence_lock); unsigned queue_index; struct amdgpu_queue *queue; uint_seq_no prev_seq_no, next_seq_no; if (!QUEUE_USES_ALT_FENCE) { queue_index = acs->queue_index; - queue = &ws->queues[queue_index]; + queue = &aws->queues[queue_index]; prev_seq_no = queue->latest_seq_no; /* Generate a per queue sequence number. The logic is similar to the kernel side amdgpu seqno, @@ -1276,10 +1276,10 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index) amdgpu_fence_reference(&tmp_fence, *oldest_fence); /* Unlock the mutex before waiting. */ - simple_mtx_unlock(&ws->bo_fence_lock); + simple_mtx_unlock(&aws->bo_fence_lock); amdgpu_fence_wait(tmp_fence, OS_TIMEOUT_INFINITE, false); amdgpu_fence_reference(&tmp_fence, NULL); - simple_mtx_lock(&ws->bo_fence_lock); + simple_mtx_lock(&aws->bo_fence_lock); } /* Remove the idle fence from the ring. */ @@ -1303,8 +1303,8 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index) struct amdgpu_fence *prev_fence = (struct amdgpu_fence*)queue->fences[prev_seq_no % AMDGPU_FENCE_RING_SIZE]; - if (prev_fence && (ws->info.ip[acs->ip_type].num_queues > 1 || queue->last_ctx != acs->ctx)) - add_seq_no_to_list(ws, &seq_no_dependencies, queue_index, prev_seq_no); + if (prev_fence && (aws->info.ip[acs->ip_type].num_queues > 1 || queue->last_ctx != acs->ctx)) + add_seq_no_to_list(aws, &seq_no_dependencies, queue_index, prev_seq_no); } /* Since the kernel driver doesn't synchronize execution between different @@ -1322,7 +1322,7 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index) struct amdgpu_cs_buffer *buffer = &slab_entry_buffers[i]; struct amdgpu_winsys_bo *bo = buffer->bo; - amdgpu_add_fences_to_dependencies(ws, cs, queue_index_bit, &seq_no_dependencies, bo, + amdgpu_add_fences_to_dependencies(aws, cs, queue_index_bit, &seq_no_dependencies, bo, buffer->usage); if (QUEUE_USES_ALT_FENCE) amdgpu_fence_reference(&bo->alt_fence, cs->fence); @@ -1350,7 +1350,7 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index) struct amdgpu_cs_buffer *buffer = &sparse_buffers[i]; struct amdgpu_winsys_bo *bo = buffer->bo; - amdgpu_add_fences_to_dependencies(ws, cs, queue_index_bit, &seq_no_dependencies, bo, + amdgpu_add_fences_to_dependencies(aws, cs, queue_index_bit, &seq_no_dependencies, bo, buffer->usage); if (QUEUE_USES_ALT_FENCE) amdgpu_fence_reference(&bo->alt_fence, cs->fence); @@ -1395,7 +1395,7 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index) struct amdgpu_cs_buffer *buffer = &real_buffers[i]; struct amdgpu_winsys_bo *bo = buffer->bo; - amdgpu_add_fences_to_dependencies(ws, cs, queue_index_bit, &seq_no_dependencies, bo, + amdgpu_add_fences_to_dependencies(aws, cs, queue_index_bit, &seq_no_dependencies, bo, buffer->usage); if (QUEUE_USES_ALT_FENCE) amdgpu_fence_reference(&bo->alt_fence, cs->fence); @@ -1442,7 +1442,7 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index) bool valid = seq_no_dependencies.valid_fence_mask & BITFIELD_BIT(i); uint_seq_no old = seq_no_dependencies.seq_no[i]; - add_seq_no_to_list(ws, &seq_no_dependencies, i, ws->queues[i].latest_seq_no); + add_seq_no_to_list(aws, &seq_no_dependencies, i, aws->queues[i].latest_seq_no); uint_seq_no new = seq_no_dependencies.seq_no[i]; if (!valid) @@ -1456,7 +1456,7 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index) /* Convert the sequence numbers we gathered to fence dependencies. */ u_foreach_bit(i, seq_no_dependencies.valid_fence_mask) { - struct pipe_fence_handle **fence = get_fence_from_ring(ws, &seq_no_dependencies, i); + struct pipe_fence_handle **fence = get_fence_from_ring(aws, &seq_no_dependencies, i); if (fence) { /* If it's idle, don't add it to the list of dependencies. */ @@ -1476,30 +1476,30 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index) /* Update the last used context in the queue. */ amdgpu_ctx_reference(&queue->last_ctx, acs->ctx); } - simple_mtx_unlock(&ws->bo_fence_lock); + simple_mtx_unlock(&aws->bo_fence_lock); #ifdef DEBUG /* Prepare the buffer list. */ - if (ws->debug_all_bos) { + if (aws->debug_all_bos) { /* The buffer list contains all buffers. This is a slow path that * ensures that no buffer is missing in the BO list. */ - simple_mtx_lock(&ws->global_bo_list_lock); + simple_mtx_lock(&aws->global_bo_list_lock); bo_list = (struct drm_amdgpu_bo_list_entry *) - alloca(ws->num_buffers * sizeof(struct drm_amdgpu_bo_list_entry)); + alloca(aws->num_buffers * sizeof(struct drm_amdgpu_bo_list_entry)); num_real_buffers = 0; - list_for_each_entry(struct amdgpu_bo_real, bo, &ws->global_bo_list, global_list_item) { + list_for_each_entry(struct amdgpu_bo_real, bo, &aws->global_bo_list, global_list_item) { bo_list[num_real_buffers].bo_handle = bo->kms_handle; bo_list[num_real_buffers].bo_priority = 0; ++num_real_buffers; } - simple_mtx_unlock(&ws->global_bo_list_lock); + simple_mtx_unlock(&aws->global_bo_list_lock); } #endif if (acs->ip_type == AMD_IP_GFX) - ws->gfx_bo_list_counter += num_real_buffers; + aws->gfx_bo_list_counter += num_real_buffers; struct drm_amdgpu_cs_chunk chunks[8]; unsigned num_chunks = 0; @@ -1557,7 +1557,7 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index) chunks[num_chunks].chunk_data = (uintptr_t)sem_chunk; num_chunks++; - if (ws->info.has_fw_based_shadowing && acs->mcbp_fw_shadow_chunk.shadow_va) { + if (aws->info.has_fw_based_shadowing && acs->mcbp_fw_shadow_chunk.shadow_va) { chunks[num_chunks].chunk_id = AMDGPU_CHUNK_ID_CP_GFX_SHADOW; chunks[num_chunks].length_dw = sizeof(struct drm_amdgpu_cs_chunk_cp_gfx_shadow) / 4; chunks[num_chunks].chunk_data = (uintptr_t)&acs->mcbp_fw_shadow_chunk; @@ -1599,7 +1599,7 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index) if (noop && acs->ip_type == AMD_IP_GFX) { /* Reduce the IB size and fill it with NOP to make it like an empty IB. */ - unsigned noop_dw_size = ws->info.ip[AMD_IP_GFX].ib_pad_dw_mask + 1; + unsigned noop_dw_size = aws->info.ip[AMD_IP_GFX].ib_pad_dw_mask + 1; assert(cs->chunk_ib[IB_MAIN].ib_bytes / 4 >= noop_dw_size); cs->ib_main_addr[0] = PKT3(PKT3_NOP, noop_dw_size - 2, 0); @@ -1629,7 +1629,7 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index) if (r == -ENOMEM) os_time_sleep(1000); - r = amdgpu_cs_submit_raw2(ws->dev, acs->ctx->ctx, 0, num_chunks, chunks, &seq_no); + r = amdgpu_cs_submit_raw2(aws->dev, acs->ctx->ctx, 0, num_chunks, chunks, &seq_no); } while (r == -ENOMEM); if (!r) { @@ -1672,7 +1672,7 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index) if (r || noop) amdgpu_fence_signalled(cs->fence); - if (unlikely(ws->info.has_fw_based_shadowing && acs->mcbp_fw_shadow_chunk.flags && r == 0)) + if (unlikely(aws->info.has_fw_based_shadowing && acs->mcbp_fw_shadow_chunk.flags && r == 0)) acs->mcbp_fw_shadow_chunk.flags = 0; cs->error_code = r; @@ -1690,25 +1690,25 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index) /* Regular real BOs. */ for (unsigned i = 0; i < initial_num_real_buffers; i++) { p_atomic_dec(&buffers[i].bo->num_active_ioctls); - amdgpu_winsys_bo_drop_reference(ws, buffers[i].bo); + amdgpu_winsys_bo_drop_reference(aws, buffers[i].bo); } /* Do nothing for slab BOs. */ /* Sparse backing BOs. */ for (unsigned i = num_real_buffers_except_sparse; i < num_buffers; i++) - amdgpu_winsys_bo_drop_reference(ws, buffers[i].bo); + amdgpu_winsys_bo_drop_reference(aws, buffers[i].bo); } else { for (unsigned i = 0; i < num_buffers; i++) { p_atomic_dec(&buffers[i].bo->num_active_ioctls); - amdgpu_winsys_bo_drop_reference(ws, buffers[i].bo); + amdgpu_winsys_bo_drop_reference(aws, buffers[i].bo); } } cs->buffer_lists[list].num_buffers = 0; } - amdgpu_cs_context_cleanup(ws, cs); + amdgpu_cs_context_cleanup(aws, cs); } /* Make sure the previous submission is completed. */ @@ -1725,16 +1725,16 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs, struct pipe_fence_handle **fence) { struct amdgpu_cs *cs = amdgpu_cs(rcs); - struct amdgpu_winsys *ws = cs->ws; + struct amdgpu_winsys *aws = cs->aws; int error_code = 0; - uint32_t ib_pad_dw_mask = ws->info.ip[cs->ip_type].ib_pad_dw_mask; + uint32_t ib_pad_dw_mask = aws->info.ip[cs->ip_type].ib_pad_dw_mask; rcs->current.max_dw += amdgpu_cs_epilog_dws(cs); /* Pad the IB according to the mask. */ switch (cs->ip_type) { case AMD_IP_SDMA: - if (ws->info.gfx_level <= GFX6) { + if (aws->info.gfx_level <= GFX6) { while (rcs->current.cdw & ib_pad_dw_mask) radeon_emit(rcs, 0xf0000000); /* NOP packet */ } else { @@ -1744,9 +1744,9 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs, break; case AMD_IP_GFX: case AMD_IP_COMPUTE: - amdgpu_pad_gfx_compute_ib(ws, cs->ip_type, rcs->current.buf, &rcs->current.cdw, 0); + amdgpu_pad_gfx_compute_ib(aws, cs->ip_type, rcs->current.buf, &rcs->current.cdw, 0); if (cs->ip_type == AMD_IP_GFX) - ws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) * 4; + aws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) * 4; break; case AMD_IP_UVD: case AMD_IP_UVD_ENC: @@ -1780,7 +1780,7 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs, struct amdgpu_cs_context *cur = cs->csc; /* Set IB sizes. */ - amdgpu_ib_finalize(ws, rcs, &cs->main_ib, cs->ip_type); + amdgpu_ib_finalize(aws, rcs, &cs->main_ib, cs->ip_type); /* Create a fence. */ amdgpu_fence_reference(&cur->fence, NULL); @@ -1809,7 +1809,7 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs, cs->cst = cur; /* Submit. */ - util_queue_add_job(&ws->cs_queue, cs, &cs->flush_completed, + util_queue_add_job(&aws->cs_queue, cs, &cs->flush_completed, cs->uses_alt_fence ? amdgpu_cs_submit_ib : amdgpu_cs_submit_ib, NULL, 0); @@ -1826,13 +1826,13 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs, if (flags & RADEON_FLUSH_TOGGLE_SECURE_SUBMISSION) cs->csc->secure = !cs->csc->secure; - amdgpu_cs_context_cleanup_buffers(ws, cs->csc); - amdgpu_cs_context_cleanup(ws, cs->csc); + amdgpu_cs_context_cleanup_buffers(aws, cs->csc); + amdgpu_cs_context_cleanup(aws, cs->csc); } memset(cs->csc->buffer_indices_hashlist, -1, sizeof(cs->buffer_indices_hashlist)); - amdgpu_get_new_ib(ws, rcs, &cs->main_ib, cs); + amdgpu_get_new_ib(aws, rcs, &cs->main_ib, cs); if (cs->preamble_ib_bo) { amdgpu_cs_add_buffer(rcs, cs->preamble_ib_bo, @@ -1840,9 +1840,9 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs, } if (cs->ip_type == AMD_IP_GFX) - ws->num_gfx_IBs++; + aws->num_gfx_IBs++; else if (cs->ip_type == AMD_IP_SDMA) - ws->num_sdma_IBs++; + aws->num_sdma_IBs++; return error_code; } @@ -1856,12 +1856,12 @@ static void amdgpu_cs_destroy(struct radeon_cmdbuf *rcs) amdgpu_cs_sync_flush(rcs); util_queue_fence_destroy(&cs->flush_completed); - p_atomic_dec(&cs->ws->num_cs); - radeon_bo_reference(&cs->ws->dummy_sws.base, &cs->preamble_ib_bo, NULL); - radeon_bo_reference(&cs->ws->dummy_sws.base, &cs->main_ib.big_buffer, NULL); + p_atomic_dec(&cs->aws->num_cs); + radeon_bo_reference(&cs->aws->dummy_sws.base, &cs->preamble_ib_bo, NULL); + radeon_bo_reference(&cs->aws->dummy_sws.base, &cs->main_ib.big_buffer, NULL); FREE(rcs->prev); - amdgpu_destroy_cs_context(cs->ws, &cs->csc1); - amdgpu_destroy_cs_context(cs->ws, &cs->csc2); + amdgpu_destroy_cs_context(cs->aws, &cs->csc1); + amdgpu_destroy_cs_context(cs->aws, &cs->csc2); amdgpu_fence_reference(&cs->next_fence, NULL); FREE(cs); } diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h index ca79b5373f6..60d9c409600 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h @@ -24,7 +24,7 @@ extern "C" { struct amdgpu_ctx { struct pipe_reference reference; - struct amdgpu_winsys *ws; + struct amdgpu_winsys *aws; amdgpu_context_handle ctx; amdgpu_bo_handle user_fence_bo; uint64_t *user_fence_cpu_address_base; @@ -87,7 +87,7 @@ struct amdgpu_cs_context { struct drm_amdgpu_cs_chunk_ib chunk_ib[IB_NUM]; uint32_t *ib_main_addr; /* the beginning of IB before chaining */ - struct amdgpu_winsys *ws; + struct amdgpu_winsys *aws; /* Buffers. */ struct amdgpu_buffer_list buffer_lists[NUM_BO_LIST_TYPES]; @@ -115,7 +115,7 @@ struct amdgpu_cs_context { struct amdgpu_cs { struct amdgpu_ib main_ib; /* must be first because this is inherited */ - struct amdgpu_winsys *ws; + struct amdgpu_winsys *aws; struct amdgpu_ctx *ctx; /* @@ -164,7 +164,7 @@ struct amdgpu_fence { struct pipe_reference reference; uint32_t syncobj; - struct amdgpu_winsys *ws; + struct amdgpu_winsys *aws; /* The following field aren't set for imported fences. */ struct amdgpu_ctx *ctx; /* submission context */ diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c index 5be6e55d2e1..856371fb2e9 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c @@ -47,7 +47,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws, enum radeon_surf_mode mode, struct radeon_surf *surf) { - struct amdgpu_winsys *ws = amdgpu_winsys(rws); + struct amdgpu_winsys *aws = amdgpu_winsys(rws); int r; r = amdgpu_surface_sanity(tex); @@ -81,14 +81,14 @@ static int amdgpu_surface_init(struct radeon_winsys *rws, * always use consecutive surface indices when FMASK is allocated between * them. */ - config.info.surf_index = &ws->surf_index_color; - config.info.fmask_surf_index = &ws->surf_index_fmask; + config.info.surf_index = &aws->surf_index_color; + config.info.fmask_surf_index = &aws->surf_index_fmask; if (flags & RADEON_SURF_Z_OR_SBUFFER) config.info.surf_index = NULL; /* Use radeon_info from the driver, not the winsys. The driver is allowed to change it. */ - return ac_compute_surface(ws->addrlib, info, &config, mode, surf); + return ac_compute_surface(aws->addrlib, info, &config, mode, surf); } void amdgpu_surface_init_functions(struct amdgpu_screen_winsys *sws) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c index aa349e2cbe4..b7f1c0bbb66 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c @@ -31,78 +31,78 @@ DEBUG_GET_ONCE_BOOL_OPTION(all_bos, "RADEON_ALL_BOS", false) #endif /* Helper function to do the ioctls needed for setup and init. */ -static bool do_winsys_init(struct amdgpu_winsys *ws, +static bool do_winsys_init(struct amdgpu_winsys *aws, const struct pipe_screen_config *config, int fd) { - if (!ac_query_gpu_info(fd, ws->dev, &ws->info, false)) + if (!ac_query_gpu_info(fd, aws->dev, &aws->info, false)) goto fail; /* TODO: Enable this once the kernel handles it efficiently. */ - if (ws->info.has_dedicated_vram) - ws->info.has_local_buffers = false; + if (aws->info.has_dedicated_vram) + aws->info.has_local_buffers = false; - ws->addrlib = ac_addrlib_create(&ws->info, &ws->info.max_alignment); - if (!ws->addrlib) { + aws->addrlib = ac_addrlib_create(&aws->info, &aws->info.max_alignment); + if (!aws->addrlib) { fprintf(stderr, "amdgpu: Cannot create addrlib.\n"); goto fail; } - ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL || + aws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL || strstr(debug_get_option("AMD_DEBUG", ""), "check_vm") != NULL; - ws->noop_cs = ws->info.family_overridden || debug_get_bool_option("RADEON_NOOP", false); + aws->noop_cs = aws->info.family_overridden || debug_get_bool_option("RADEON_NOOP", false); #ifdef DEBUG - ws->debug_all_bos = debug_get_option_all_bos(); + aws->debug_all_bos = debug_get_option_all_bos(); #endif - ws->reserve_vmid = strstr(debug_get_option("R600_DEBUG", ""), "reserve_vmid") != NULL || + aws->reserve_vmid = strstr(debug_get_option("R600_DEBUG", ""), "reserve_vmid") != NULL || strstr(debug_get_option("AMD_DEBUG", ""), "reserve_vmid") != NULL || strstr(debug_get_option("AMD_DEBUG", ""), "sqtt") != NULL; - ws->zero_all_vram_allocs = strstr(debug_get_option("R600_DEBUG", ""), "zerovram") != NULL || + aws->zero_all_vram_allocs = strstr(debug_get_option("R600_DEBUG", ""), "zerovram") != NULL || driQueryOptionb(config->options, "radeonsi_zerovram"); return true; fail: - amdgpu_device_deinitialize(ws->dev); - ws->dev = NULL; + amdgpu_device_deinitialize(aws->dev); + aws->dev = NULL; return false; } -static void do_winsys_deinit(struct amdgpu_winsys *ws) +static void do_winsys_deinit(struct amdgpu_winsys *aws) { - if (ws->reserve_vmid) - amdgpu_vm_unreserve_vmid(ws->dev, 0); + if (aws->reserve_vmid) + amdgpu_vm_unreserve_vmid(aws->dev, 0); - for (unsigned i = 0; i < ARRAY_SIZE(ws->queues); i++) { - for (unsigned j = 0; j < ARRAY_SIZE(ws->queues[i].fences); j++) - amdgpu_fence_reference(&ws->queues[i].fences[j], NULL); + for (unsigned i = 0; i < ARRAY_SIZE(aws->queues); i++) { + for (unsigned j = 0; j < ARRAY_SIZE(aws->queues[i].fences); j++) + amdgpu_fence_reference(&aws->queues[i].fences[j], NULL); - amdgpu_ctx_reference(&ws->queues[i].last_ctx, NULL); + amdgpu_ctx_reference(&aws->queues[i].last_ctx, NULL); } - if (util_queue_is_initialized(&ws->cs_queue)) - util_queue_destroy(&ws->cs_queue); + if (util_queue_is_initialized(&aws->cs_queue)) + util_queue_destroy(&aws->cs_queue); - simple_mtx_destroy(&ws->bo_fence_lock); - if (ws->bo_slabs.groups) - pb_slabs_deinit(&ws->bo_slabs); - pb_cache_deinit(&ws->bo_cache); - _mesa_hash_table_destroy(ws->bo_export_table, NULL); - simple_mtx_destroy(&ws->sws_list_lock); + simple_mtx_destroy(&aws->bo_fence_lock); + if (aws->bo_slabs.groups) + pb_slabs_deinit(&aws->bo_slabs); + pb_cache_deinit(&aws->bo_cache); + _mesa_hash_table_destroy(aws->bo_export_table, NULL); + simple_mtx_destroy(&aws->sws_list_lock); #ifdef DEBUG - simple_mtx_destroy(&ws->global_bo_list_lock); + simple_mtx_destroy(&aws->global_bo_list_lock); #endif - simple_mtx_destroy(&ws->bo_export_table_lock); + simple_mtx_destroy(&aws->bo_export_table_lock); - ac_addrlib_destroy(ws->addrlib); - amdgpu_device_deinitialize(ws->dev); - FREE(ws); + ac_addrlib_destroy(aws->addrlib); + amdgpu_device_deinitialize(aws->dev); + FREE(aws); } static void amdgpu_winsys_destroy_locked(struct radeon_winsys *rws, bool locked) { struct amdgpu_screen_winsys *sws = amdgpu_screen_winsys(rws); - struct amdgpu_winsys *ws = sws->aws; + struct amdgpu_winsys *aws = sws->aws; bool destroy; /* When the reference counter drops to zero, remove the device pointer @@ -114,9 +114,9 @@ static void amdgpu_winsys_destroy_locked(struct radeon_winsys *rws, bool locked) if (!locked) simple_mtx_lock(&dev_tab_mutex); - destroy = pipe_reference(&ws->reference, NULL); + destroy = pipe_reference(&aws->reference, NULL); if (destroy && dev_tab) { - _mesa_hash_table_remove_key(dev_tab, ws->dev); + _mesa_hash_table_remove_key(dev_tab, aws->dev); if (_mesa_hash_table_num_entries(dev_tab) == 0) { _mesa_hash_table_destroy(dev_tab, NULL); dev_tab = NULL; @@ -127,7 +127,7 @@ static void amdgpu_winsys_destroy_locked(struct radeon_winsys *rws, bool locked) simple_mtx_unlock(&dev_tab_mutex); if (destroy) - do_winsys_deinit(ws); + do_winsys_deinit(aws); close(sws->fd); FREE(rws); @@ -140,9 +140,9 @@ static void amdgpu_winsys_destroy(struct radeon_winsys *rws) static void amdgpu_winsys_query_info(struct radeon_winsys *rws, struct radeon_info *info) { - struct amdgpu_winsys *ws = amdgpu_winsys(rws); + struct amdgpu_winsys *aws = amdgpu_winsys(rws); - *info = ws->info; + *info = aws->info; } static bool amdgpu_cs_request_feature(struct radeon_cmdbuf *rcs, @@ -155,68 +155,68 @@ static bool amdgpu_cs_request_feature(struct radeon_cmdbuf *rcs, static uint64_t amdgpu_query_value(struct radeon_winsys *rws, enum radeon_value_id value) { - struct amdgpu_winsys *ws = amdgpu_winsys(rws); + struct amdgpu_winsys *aws = amdgpu_winsys(rws); struct amdgpu_heap_info heap; uint64_t retval = 0; switch (value) { case RADEON_REQUESTED_VRAM_MEMORY: - return ws->allocated_vram; + return aws->allocated_vram; case RADEON_REQUESTED_GTT_MEMORY: - return ws->allocated_gtt; + return aws->allocated_gtt; case RADEON_MAPPED_VRAM: - return ws->mapped_vram; + return aws->mapped_vram; case RADEON_MAPPED_GTT: - return ws->mapped_gtt; + return aws->mapped_gtt; case RADEON_SLAB_WASTED_VRAM: - return ws->slab_wasted_vram; + return aws->slab_wasted_vram; case RADEON_SLAB_WASTED_GTT: - return ws->slab_wasted_gtt; + return aws->slab_wasted_gtt; case RADEON_BUFFER_WAIT_TIME_NS: - return ws->buffer_wait_time; + return aws->buffer_wait_time; case RADEON_NUM_MAPPED_BUFFERS: - return ws->num_mapped_buffers; + return aws->num_mapped_buffers; case RADEON_TIMESTAMP: - amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval); + amdgpu_query_info(aws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval); return retval; case RADEON_NUM_GFX_IBS: - return ws->num_gfx_IBs; + return aws->num_gfx_IBs; case RADEON_NUM_SDMA_IBS: - return ws->num_sdma_IBs; + return aws->num_sdma_IBs; case RADEON_GFX_BO_LIST_COUNTER: - return ws->gfx_bo_list_counter; + return aws->gfx_bo_list_counter; case RADEON_GFX_IB_SIZE_COUNTER: - return ws->gfx_ib_size_counter; + return aws->gfx_ib_size_counter; case RADEON_NUM_BYTES_MOVED: - amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval); + amdgpu_query_info(aws->dev, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval); return retval; case RADEON_NUM_EVICTIONS: - amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_EVICTIONS, 8, &retval); + amdgpu_query_info(aws->dev, AMDGPU_INFO_NUM_EVICTIONS, 8, &retval); return retval; case RADEON_NUM_VRAM_CPU_PAGE_FAULTS: - amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS, 8, &retval); + amdgpu_query_info(aws->dev, AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS, 8, &retval); return retval; case RADEON_VRAM_USAGE: - amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap); + amdgpu_query_heap_info(aws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap); return heap.heap_usage; case RADEON_VRAM_VIS_USAGE: - amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, + amdgpu_query_heap_info(aws->dev, AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &heap); return heap.heap_usage; case RADEON_GTT_USAGE: - amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &heap); + amdgpu_query_heap_info(aws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &heap); return heap.heap_usage; case RADEON_GPU_TEMPERATURE: - amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GPU_TEMP, 4, &retval); + amdgpu_query_sensor_info(aws->dev, AMDGPU_INFO_SENSOR_GPU_TEMP, 4, &retval); return retval; case RADEON_CURRENT_SCLK: - amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_SCLK, 4, &retval); + amdgpu_query_sensor_info(aws->dev, AMDGPU_INFO_SENSOR_GFX_SCLK, 4, &retval); return retval; case RADEON_CURRENT_MCLK: - amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_MCLK, 4, &retval); + amdgpu_query_sensor_info(aws->dev, AMDGPU_INFO_SENSOR_GFX_MCLK, 4, &retval); return retval; case RADEON_CS_THREAD_TIME: - return util_queue_get_thread_time_nano(&ws->cs_queue, 0); + return util_queue_get_thread_time_nano(&aws->cs_queue, 0); } return 0; } @@ -225,9 +225,9 @@ static bool amdgpu_read_registers(struct radeon_winsys *rws, unsigned reg_offset, unsigned num_registers, uint32_t *out) { - struct amdgpu_winsys *ws = amdgpu_winsys(rws); + struct amdgpu_winsys *aws = amdgpu_winsys(rws); - return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers, + return amdgpu_read_mm_registers(aws->dev, reg_offset / 4, num_registers, 0xffffffff, 0, out) == 0; } @@ -273,9 +273,9 @@ static bool amdgpu_winsys_unref(struct radeon_winsys *rws) static void amdgpu_pin_threads_to_L3_cache(struct radeon_winsys *rws, unsigned cpu) { - struct amdgpu_winsys *ws = amdgpu_winsys(rws); + struct amdgpu_winsys *aws = amdgpu_winsys(rws); - util_thread_sched_apply_policy(ws->cs_queue.threads[0], + util_thread_sched_apply_policy(aws->cs_queue.threads[0], UTIL_THREAD_DRIVER_SUBMIT, cpu, NULL); }