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rusticl/spirv: properly set float execution mode at spirv_to_nir time

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Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41703>
This commit is contained in:
Karol Herbst 2026-05-20 01:55:01 +02:00 • committed by Marge Bot
parent e6ed0094af
commit 5a8d4b28b5
5 changed files with 10 additions and 25 deletions
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7
src/gallium/frontends/rusticl/core/device.rs
View file

@ -1389,9 +1389,16 @@ impl DeviceBase {
}
pub fn spirv_to_nir_opts(&self) -> SPIRVToNirOptions {
let spirv_float_controls = float_controls::FLOAT_CONTROLS_DENORM_PRESERVE_FP16
| float_controls::FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
| float_controls::FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| float_controls::FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
| float_controls::FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64;
SPIRVToNirOptions {
caps: &self.spirv_caps,
address_bits: self.address_bits(),
float_controls: spirv_float_controls,
}
}
}

7
src/gallium/frontends/rusticl/core/kernel.rs
View file

@ -698,13 +698,6 @@ fn compile_nir_to_args(
args: &[spirv::SPIRVKernelArg],
lib_clc: &NirShader,
) -> (Vec<KernelArg>, NirShader) {
// this is a hack until we support fp16 properly and check for denorms inside vstore/vload_half
nir.preserve_fp16_denorms();
// Set to rtne for now until drivers are able to report their preferred rounding mode, that also
// matches what we report via the API.
nir.set_fp_rounding_mode_rtne();
nir_pass!(nir, nir_scale_fdiv);
nir.structurize();
nir_pass!(

4
src/gallium/frontends/rusticl/mesa/compiler/clc/spirv.rs
View file

@ -93,6 +93,7 @@ fn create_clc_logger(msgs: &mut Vec<String>) -> clc_logger {
pub struct SPIRVToNirOptions<'a> {
pub caps: &'a spirv_capabilities,
pub address_bits: u32,
pub float_controls: float_controls,
}
impl SPIRVBin {
@ -305,12 +306,11 @@ impl SPIRVBin {
private_data: ptr::from_mut(log).cast(),
});
let float_controls = float_controls::FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32 as u32;
spirv_to_nir_options {
create_library: library,
environment: nir_spirv_execution_environment::NIR_SPIRV_OPENCL,
clc_shader: clc_shader,
float_controls_execution_mode: float_controls,
float_controls_execution_mode: options.float_controls.0,
printf: true,
capabilities: options.caps,
constant_addr_format: global_addr_format,

16
src/gallium/frontends/rusticl/mesa/compiler/nir.rs
View file

@ -471,22 +471,6 @@ impl NirShader {
}
}
pub fn preserve_fp16_denorms(&mut self) {
unsafe {
self.nir.as_mut().info.float_controls_execution_mode |=
float_controls::FLOAT_CONTROLS_DENORM_PRESERVE_FP16 as u32;
}
}
pub fn set_fp_rounding_mode_rtne(&mut self) {
unsafe {
self.nir.as_mut().info.float_controls_execution_mode |=
float_controls::FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 as u32
| float_controls::FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32 as u32
| float_controls::FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64 as u32;
}
}
pub fn reads_sysval(&self, sysval: gl_system_value) -> bool {
let nir = unsafe { self.nir.as_ref() };
bitset::test_bit(&nir.info.system_values_read, sysval as u32)

1
src/gallium/frontends/rusticl/meson.build
View file

@ -308,6 +308,7 @@ rusticl_mesa_bindings = rust.bindgen(
'--bitfield-enum', 'nir_lower_int64_options',
'--bitfield-enum', 'nir_opt_if_options',
'--bitfield-enum', 'nir_variable_mode',
'--bitfield-enum', 'float_controls',
'--allowlist-function', 'should_.*_nir',
'--allowlist-function', 'spirv_.*',