From 5a8d4b28b5d7593a8bd4da90a83f5d25926cfb03 Mon Sep 17 00:00:00 2001 From: Karol Herbst Date: Wed, 20 May 2026 01:55:01 +0200 Subject: [PATCH] rusticl/spirv: properly set float execution mode at spirv_to_nir time Reviewed-by: Adam Jackson Part-of: --- src/gallium/frontends/rusticl/core/device.rs | 7 +++++++ src/gallium/frontends/rusticl/core/kernel.rs | 7 ------- .../frontends/rusticl/mesa/compiler/clc/spirv.rs | 4 ++-- .../frontends/rusticl/mesa/compiler/nir.rs | 16 ---------------- src/gallium/frontends/rusticl/meson.build | 1 + 5 files changed, 10 insertions(+), 25 deletions(-) diff --git a/src/gallium/frontends/rusticl/core/device.rs b/src/gallium/frontends/rusticl/core/device.rs index cff0bfefbc7..85aa646009d 100644 --- a/src/gallium/frontends/rusticl/core/device.rs +++ b/src/gallium/frontends/rusticl/core/device.rs @@ -1389,9 +1389,16 @@ impl DeviceBase { } pub fn spirv_to_nir_opts(&self) -> SPIRVToNirOptions { + let spirv_float_controls = float_controls::FLOAT_CONTROLS_DENORM_PRESERVE_FP16 + | float_controls::FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32 + | float_controls::FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 + | float_controls::FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32 + | float_controls::FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64; + SPIRVToNirOptions { caps: &self.spirv_caps, address_bits: self.address_bits(), + float_controls: spirv_float_controls, } } } diff --git a/src/gallium/frontends/rusticl/core/kernel.rs b/src/gallium/frontends/rusticl/core/kernel.rs index f3b0fd8cdb9..854529e5d4b 100644 --- a/src/gallium/frontends/rusticl/core/kernel.rs +++ b/src/gallium/frontends/rusticl/core/kernel.rs @@ -698,13 +698,6 @@ fn compile_nir_to_args( args: &[spirv::SPIRVKernelArg], lib_clc: &NirShader, ) -> (Vec, NirShader) { - // this is a hack until we support fp16 properly and check for denorms inside vstore/vload_half - nir.preserve_fp16_denorms(); - - // Set to rtne for now until drivers are able to report their preferred rounding mode, that also - // matches what we report via the API. - nir.set_fp_rounding_mode_rtne(); - nir_pass!(nir, nir_scale_fdiv); nir.structurize(); nir_pass!( diff --git a/src/gallium/frontends/rusticl/mesa/compiler/clc/spirv.rs b/src/gallium/frontends/rusticl/mesa/compiler/clc/spirv.rs index ee4da16f12d..41ff547cb07 100644 --- a/src/gallium/frontends/rusticl/mesa/compiler/clc/spirv.rs +++ b/src/gallium/frontends/rusticl/mesa/compiler/clc/spirv.rs @@ -93,6 +93,7 @@ fn create_clc_logger(msgs: &mut Vec) -> clc_logger { pub struct SPIRVToNirOptions<'a> { pub caps: &'a spirv_capabilities, pub address_bits: u32, + pub float_controls: float_controls, } impl SPIRVBin { @@ -305,12 +306,11 @@ impl SPIRVBin { private_data: ptr::from_mut(log).cast(), }); - let float_controls = float_controls::FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32 as u32; spirv_to_nir_options { create_library: library, environment: nir_spirv_execution_environment::NIR_SPIRV_OPENCL, clc_shader: clc_shader, - float_controls_execution_mode: float_controls, + float_controls_execution_mode: options.float_controls.0, printf: true, capabilities: options.caps, constant_addr_format: global_addr_format, diff --git a/src/gallium/frontends/rusticl/mesa/compiler/nir.rs b/src/gallium/frontends/rusticl/mesa/compiler/nir.rs index 6fa07948d4d..baeb04513a2 100644 --- a/src/gallium/frontends/rusticl/mesa/compiler/nir.rs +++ b/src/gallium/frontends/rusticl/mesa/compiler/nir.rs @@ -471,22 +471,6 @@ impl NirShader { } } - pub fn preserve_fp16_denorms(&mut self) { - unsafe { - self.nir.as_mut().info.float_controls_execution_mode |= - float_controls::FLOAT_CONTROLS_DENORM_PRESERVE_FP16 as u32; - } - } - - pub fn set_fp_rounding_mode_rtne(&mut self) { - unsafe { - self.nir.as_mut().info.float_controls_execution_mode |= - float_controls::FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 as u32 - | float_controls::FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32 as u32 - | float_controls::FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64 as u32; - } - } - pub fn reads_sysval(&self, sysval: gl_system_value) -> bool { let nir = unsafe { self.nir.as_ref() }; bitset::test_bit(&nir.info.system_values_read, sysval as u32) diff --git a/src/gallium/frontends/rusticl/meson.build b/src/gallium/frontends/rusticl/meson.build index 4885b5c80eb..41f6d8b2233 100644 --- a/src/gallium/frontends/rusticl/meson.build +++ b/src/gallium/frontends/rusticl/meson.build @@ -308,6 +308,7 @@ rusticl_mesa_bindings = rust.bindgen( '--bitfield-enum', 'nir_lower_int64_options', '--bitfield-enum', 'nir_opt_if_options', '--bitfield-enum', 'nir_variable_mode', + '--bitfield-enum', 'float_controls', '--allowlist-function', 'should_.*_nir', '--allowlist-function', 'spirv_.*',