fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-02-22 22:50:32 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

freedreno/a3-5xx: Don't try to emit ISAM for SSBO loads.

Browse source 
We don't emit tex descriptors for the SSBOs, so if we took this path we'd
fault.

Fixes: 75eb0d2891 ("freedreno/ir3: Allow isam for non-bindless ssbo loads")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24682>
This commit is contained in:
Emma Anholt 2023-08-14 16:20:34 -07:00 • committed by Marge Bot
parent 408199236f
commit 5a8672952a
5 changed files with 11 additions and 39 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

37
src/freedreno/ci/freedreno-a530-fails.txt
View file

@ -59,10 +59,6 @@ KHR-GLES31.core.internalformat.copy_tex_image.alpha,Fail
KHR-GLES31.core.draw_indirect.advanced-twoPass-transformFeedback-arrays,Fail
KHR-GLES31.core.draw_indirect.advanced-twoPass-transformFeedback-elements,Fail
KHR-GLES31.core.layout_binding.buffer_layout_binding_atomicAdd_FragmentShader,Fail
KHR-GLES31.core.shader_storage_buffer_object.basic-syntax-cs,Fail
# msm 900000.mdss: [drm:a5xx_irq] *ERROR* gpu fault ring 0 fence 2c54ef status E40801C1 rb 0162/0162 ib1 000000000104B000/0000 ib2 000000000104C000/0000
KHR-GLES31.core.texture_buffer.texture_buffer_atomic_functions,Fail
@ -348,37 +344,4 @@ spec@arb_uniform_buffer_object@execution@std140-struct-array-array-array-struct,
spec@arb_uniform_buffer_object@execution@shared-array-struct-array-struct,Fail
spec@arb_uniform_buffer_object@execution@std140-array-struct-array-struct,Fail
dEQP-GLES31.functional.compute.basic.copy_ssbo_to_image_large,Fail
dEQP-GLES31.functional.compute.basic.copy_ssbo_to_image_small,Fail
dEQP-GLES31.functional.compute.basic.image_atomic_op_local_size_1,Fail
dEQP-GLES31.functional.compute.basic.image_atomic_op_local_size_8,Fail
dEQP-GLES31.functional.compute.indirect_dispatch.gen_in_compute.multi_dispatch_reuse_command,Fail
dEQP-GLES31.functional.layout_binding.ssbo.fragment_binding_array,Fail
dEQP-GLES31.functional.layout_binding.ssbo.fragment_binding_max_array,Fail
dEQP-GLES31.functional.layout_binding.ssbo.fragment_binding_max,Fail
dEQP-GLES31.functional.layout_binding.ssbo.fragment_binding_multiple,Fail
dEQP-GLES31.functional.layout_binding.ssbo.fragment_binding_single,Fail
dEQP-GLES31.functional.shaders.opaque_type_indexing.ssbo.const_expression_fragment,Fail
dEQP-GLES31.functional.shaders.opaque_type_indexing.ssbo.const_literal_fragment,Fail
dEQP-GLES31.functional.ssbo.layout.random.all_per_block_buffers.11,Fail
dEQP-GLES31.functional.ssbo.layout.random.all_per_block_buffers.19,Fail
dEQP-GLES31.functional.ssbo.layout.random.all_per_block_buffers.23,Fail
dEQP-GLES31.functional.ssbo.layout.random.all_per_block_buffers.24,Fail
dEQP-GLES31.functional.ssbo.layout.random.basic_arrays.10,Fail
dEQP-GLES31.functional.ssbo.layout.random.basic_arrays.18,Fail
dEQP-GLES31.functional.ssbo.layout.random.basic_instance_arrays.1,Fail
dEQP-GLES31.functional.ssbo.layout.random.basic_instance_arrays.19,Fail
dEQP-GLES31.functional.ssbo.layout.random.basic_instance_arrays.23,Fail
dEQP-GLES31.functional.ssbo.layout.random.basic_types.15,Fail
dEQP-GLES31.functional.ssbo.layout.random.nested_structs_arrays_instance_arrays.13,Fail
dEQP-GLES31.functional.ssbo.layout.random.nested_structs.7,Fail
dEQP-GLES31.functional.ssbo.layout.random.nested_structs.9,Fail
dEQP-GLES31.functional.ssbo.layout.random.unsized_arrays.23,Fail
dEQP-GLES31.functional.ssbo.layout.random.vector_types.3,Fail
KHR-GLES31.core.shader_image_load_store.basic-allTargets-loadStoreCS,Fail
KHR-GLES31.core.shader_storage_buffer_object.advanced-usage-operators-cs,Fail
KHR-GLES31.core.shader_storage_buffer_object.basic-std140Layout-case3-cs,Fail
KHR-GLES31.core.shader_storage_buffer_object.basic-std430Layout-case2-cs,Fail

2
src/freedreno/ir3/ir3_compiler.c
View file

@ -219,6 +219,8 @@ ir3_compiler_create(struct fd_device *dev, const struct fd_dev_id *dev_id,
/* TODO: implement private memory on earlier gen's */
compiler->has_pvtmem = compiler->gen >= 5;
compiler->has_isam_ssbo = compiler->gen >= 6;
if (compiler->gen >= 6) {
compiler->reg_size_vec4 = dev_info->a6xx.reg_size_vec4;
} else if (compiler->gen >= 4) {

3
src/freedreno/ir3/ir3_compiler.h
View file

@ -200,6 +200,9 @@ struct ir3_compiler {
/* Whether private memory is supported */
bool has_pvtmem;
/* Whether SSBOs have descriptors for sampling with ISAM */
bool has_isam_ssbo;
/* True if 16-bit descriptors are used for both 16-bit and 32-bit access. */
bool storage_16bit;

3
src/freedreno/ir3/ir3_compiler_nir.c
View file

@ -1525,7 +1525,8 @@ emit_intrinsic_load_ssbo(struct ir3_context *ctx,
{
/* Note: isam currently can't handle vectorized loads/stores */
if (!(nir_intrinsic_access(intr) & ACCESS_CAN_REORDER) ||
intr->def.num_components > 1) {
intr->def.num_components > 1 ||
!ctx->compiler->has_isam_ssbo) {
ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
return;
}

5
src/freedreno/ir3/ir3_nir.c
View file

@ -37,13 +37,15 @@ ir3_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset,
nir_intrinsic_instr *low,
nir_intrinsic_instr *high, void *data)
{
struct ir3_compiler *compiler = data;
unsigned byte_size = bit_size / 8;
/* Don't vectorize load_ssbo's that we could otherwise lower to isam,
* as the tex cache benefit outweighs the benefit of vectorizing
*/
if ((low->intrinsic == nir_intrinsic_load_ssbo) &&
(nir_intrinsic_access(low) & ACCESS_CAN_REORDER)) {
(nir_intrinsic_access(low) & ACCESS_CAN_REORDER) &&
compiler->has_isam_ssbo) {
return false;
}
@ -158,6 +160,7 @@ ir3_optimize_loop(struct ir3_compiler *compiler, nir_shader *s)
.callback = ir3_nir_should_vectorize_mem,
.robust_modes = compiler->options.robust_buffer_access2 ?
nir_var_mem_ubo | nir_var_mem_ssbo : 0,
.cb_data = compiler,
};
progress |= OPT(s, nir_opt_load_store_vectorize, &vectorize_opts);