From 5a8672952aeab60c8abf727cbc606ef8cd014b43 Mon Sep 17 00:00:00 2001 From: Emma Anholt Date: Mon, 14 Aug 2023 16:20:34 -0700 Subject: [PATCH] freedreno/a3-5xx: Don't try to emit ISAM for SSBO loads. We don't emit tex descriptors for the SSBOs, so if we took this path we'd fault. Fixes: 75eb0d2891c2 ("freedreno/ir3: Allow isam for non-bindless ssbo loads") Part-of: --- src/freedreno/ci/freedreno-a530-fails.txt | 37 ----------------------- src/freedreno/ir3/ir3_compiler.c | 2 ++ src/freedreno/ir3/ir3_compiler.h | 3 ++ src/freedreno/ir3/ir3_compiler_nir.c | 3 +- src/freedreno/ir3/ir3_nir.c | 5 ++- 5 files changed, 11 insertions(+), 39 deletions(-) diff --git a/src/freedreno/ci/freedreno-a530-fails.txt b/src/freedreno/ci/freedreno-a530-fails.txt index 72b73418d7d..985c983bcc9 100644 --- a/src/freedreno/ci/freedreno-a530-fails.txt +++ b/src/freedreno/ci/freedreno-a530-fails.txt @@ -59,10 +59,6 @@ KHR-GLES31.core.internalformat.copy_tex_image.alpha,Fail KHR-GLES31.core.draw_indirect.advanced-twoPass-transformFeedback-arrays,Fail KHR-GLES31.core.draw_indirect.advanced-twoPass-transformFeedback-elements,Fail -KHR-GLES31.core.layout_binding.buffer_layout_binding_atomicAdd_FragmentShader,Fail - -KHR-GLES31.core.shader_storage_buffer_object.basic-syntax-cs,Fail - # msm 900000.mdss: [drm:a5xx_irq] *ERROR* gpu fault ring 0 fence 2c54ef status E40801C1 rb 0162/0162 ib1 000000000104B000/0000 ib2 000000000104C000/0000 KHR-GLES31.core.texture_buffer.texture_buffer_atomic_functions,Fail @@ -348,37 +344,4 @@ spec@arb_uniform_buffer_object@execution@std140-struct-array-array-array-struct, spec@arb_uniform_buffer_object@execution@shared-array-struct-array-struct,Fail spec@arb_uniform_buffer_object@execution@std140-array-struct-array-struct,Fail -dEQP-GLES31.functional.compute.basic.copy_ssbo_to_image_large,Fail -dEQP-GLES31.functional.compute.basic.copy_ssbo_to_image_small,Fail -dEQP-GLES31.functional.compute.basic.image_atomic_op_local_size_1,Fail -dEQP-GLES31.functional.compute.basic.image_atomic_op_local_size_8,Fail dEQP-GLES31.functional.compute.indirect_dispatch.gen_in_compute.multi_dispatch_reuse_command,Fail - -dEQP-GLES31.functional.layout_binding.ssbo.fragment_binding_array,Fail -dEQP-GLES31.functional.layout_binding.ssbo.fragment_binding_max_array,Fail -dEQP-GLES31.functional.layout_binding.ssbo.fragment_binding_max,Fail -dEQP-GLES31.functional.layout_binding.ssbo.fragment_binding_multiple,Fail -dEQP-GLES31.functional.layout_binding.ssbo.fragment_binding_single,Fail - -dEQP-GLES31.functional.shaders.opaque_type_indexing.ssbo.const_expression_fragment,Fail -dEQP-GLES31.functional.shaders.opaque_type_indexing.ssbo.const_literal_fragment,Fail -dEQP-GLES31.functional.ssbo.layout.random.all_per_block_buffers.11,Fail -dEQP-GLES31.functional.ssbo.layout.random.all_per_block_buffers.19,Fail -dEQP-GLES31.functional.ssbo.layout.random.all_per_block_buffers.23,Fail -dEQP-GLES31.functional.ssbo.layout.random.all_per_block_buffers.24,Fail -dEQP-GLES31.functional.ssbo.layout.random.basic_arrays.10,Fail -dEQP-GLES31.functional.ssbo.layout.random.basic_arrays.18,Fail -dEQP-GLES31.functional.ssbo.layout.random.basic_instance_arrays.1,Fail -dEQP-GLES31.functional.ssbo.layout.random.basic_instance_arrays.19,Fail -dEQP-GLES31.functional.ssbo.layout.random.basic_instance_arrays.23,Fail -dEQP-GLES31.functional.ssbo.layout.random.basic_types.15,Fail -dEQP-GLES31.functional.ssbo.layout.random.nested_structs_arrays_instance_arrays.13,Fail -dEQP-GLES31.functional.ssbo.layout.random.nested_structs.7,Fail -dEQP-GLES31.functional.ssbo.layout.random.nested_structs.9,Fail -dEQP-GLES31.functional.ssbo.layout.random.unsized_arrays.23,Fail -dEQP-GLES31.functional.ssbo.layout.random.vector_types.3,Fail - -KHR-GLES31.core.shader_image_load_store.basic-allTargets-loadStoreCS,Fail -KHR-GLES31.core.shader_storage_buffer_object.advanced-usage-operators-cs,Fail -KHR-GLES31.core.shader_storage_buffer_object.basic-std140Layout-case3-cs,Fail -KHR-GLES31.core.shader_storage_buffer_object.basic-std430Layout-case2-cs,Fail diff --git a/src/freedreno/ir3/ir3_compiler.c b/src/freedreno/ir3/ir3_compiler.c index 171a7a71c59..3d108ad7ab4 100644 --- a/src/freedreno/ir3/ir3_compiler.c +++ b/src/freedreno/ir3/ir3_compiler.c @@ -219,6 +219,8 @@ ir3_compiler_create(struct fd_device *dev, const struct fd_dev_id *dev_id, /* TODO: implement private memory on earlier gen's */ compiler->has_pvtmem = compiler->gen >= 5; + compiler->has_isam_ssbo = compiler->gen >= 6; + if (compiler->gen >= 6) { compiler->reg_size_vec4 = dev_info->a6xx.reg_size_vec4; } else if (compiler->gen >= 4) { diff --git a/src/freedreno/ir3/ir3_compiler.h b/src/freedreno/ir3/ir3_compiler.h index 98b40dd049b..9eb81958424 100644 --- a/src/freedreno/ir3/ir3_compiler.h +++ b/src/freedreno/ir3/ir3_compiler.h @@ -200,6 +200,9 @@ struct ir3_compiler { /* Whether private memory is supported */ bool has_pvtmem; + /* Whether SSBOs have descriptors for sampling with ISAM */ + bool has_isam_ssbo; + /* True if 16-bit descriptors are used for both 16-bit and 32-bit access. */ bool storage_16bit; diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index e1e15f83e6a..e2accd29327 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -1525,7 +1525,8 @@ emit_intrinsic_load_ssbo(struct ir3_context *ctx, { /* Note: isam currently can't handle vectorized loads/stores */ if (!(nir_intrinsic_access(intr) & ACCESS_CAN_REORDER) || - intr->def.num_components > 1) { + intr->def.num_components > 1 || + !ctx->compiler->has_isam_ssbo) { ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst); return; } diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c index a70a48cd8b6..a869bfcadec 100644 --- a/src/freedreno/ir3/ir3_nir.c +++ b/src/freedreno/ir3/ir3_nir.c @@ -37,13 +37,15 @@ ir3_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset, nir_intrinsic_instr *low, nir_intrinsic_instr *high, void *data) { + struct ir3_compiler *compiler = data; unsigned byte_size = bit_size / 8; /* Don't vectorize load_ssbo's that we could otherwise lower to isam, * as the tex cache benefit outweighs the benefit of vectorizing */ if ((low->intrinsic == nir_intrinsic_load_ssbo) && - (nir_intrinsic_access(low) & ACCESS_CAN_REORDER)) { + (nir_intrinsic_access(low) & ACCESS_CAN_REORDER) && + compiler->has_isam_ssbo) { return false; } @@ -158,6 +160,7 @@ ir3_optimize_loop(struct ir3_compiler *compiler, nir_shader *s) .callback = ir3_nir_should_vectorize_mem, .robust_modes = compiler->options.robust_buffer_access2 ? nir_var_mem_ubo | nir_var_mem_ssbo : 0, + .cb_data = compiler, }; progress |= OPT(s, nir_opt_load_store_vectorize, &vectorize_opts);