freedreno: switch to NIR loop unrolling

Force unroll setting based on GLSL IR settings:

   case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
   case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
   case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
   case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
      /* a2xx compiler doesn't handle indirect: */
      return is_ir3(screen) ? 1 : 0;

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16366>
This commit is contained in:
Timothy Arceri 2022-05-06 11:38:09 +10:00 committed by Marge Bot
parent 34e868d882
commit 57dee95b85
3 changed files with 7 additions and 4 deletions

View file

@ -115,7 +115,8 @@ ir3_compiler_destroy(struct ir3_compiler *compiler)
.has_isub = true, \
.force_indirect_unrolling_sampler = true, \
.lower_uniforms_to_ubo = true, \
.use_scoped_barrier = true
.use_scoped_barrier = true, \
.max_unroll_iterations = 32
static const nir_shader_compiler_options nir_options = {
COMMON_OPTIONS,
@ -133,7 +134,6 @@ static const nir_shader_compiler_options nir_options = {
static const nir_shader_compiler_options nir_options_a6xx = {
COMMON_OPTIONS,
.vectorize_io = true,
.max_unroll_iterations = 32,
.force_indirect_unrolling = nir_var_all,
.lower_wpos_pntc = true,
.lower_cs_local_index_to_id = true,
@ -287,6 +287,9 @@ ir3_compiler_create(struct fd_device *dev, const struct fd_dev_id *dev_id,
compiler->nir_options.has_sudot_4x8 = dev_info->a6xx.has_dp2acc;
} else {
compiler->nir_options = nir_options;
/* a2xx compiler doesn't handle indirect: */
if (compiler->gen <= 2)
compiler->nir_options.force_indirect_unrolling = nir_var_all;
}
if (!options->disable_cache)

View file

@ -51,6 +51,7 @@ static const nir_shader_compiler_options options = {
.lower_insert_word = true,
.force_indirect_unrolling = nir_var_all,
.force_indirect_unrolling_sampler = true,
.max_unroll_iterations = 32,
};
const nir_shader_compiler_options *

View file

@ -649,6 +649,7 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 0;
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return 1;
@ -675,8 +676,6 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
COND(has_compute(screen) && (shader == PIPE_SHADER_COMPUTE),
(1 << PIPE_SHADER_IR_NIR_SERIALIZED)) |
(1 << PIPE_SHADER_IR_TGSI);
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 32;
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) {