diff --git a/src/freedreno/ir3/ir3_compiler.c b/src/freedreno/ir3/ir3_compiler.c index db0b62b7b4b..e7008be2034 100644 --- a/src/freedreno/ir3/ir3_compiler.c +++ b/src/freedreno/ir3/ir3_compiler.c @@ -115,7 +115,8 @@ ir3_compiler_destroy(struct ir3_compiler *compiler) .has_isub = true, \ .force_indirect_unrolling_sampler = true, \ .lower_uniforms_to_ubo = true, \ - .use_scoped_barrier = true + .use_scoped_barrier = true, \ + .max_unroll_iterations = 32 static const nir_shader_compiler_options nir_options = { COMMON_OPTIONS, @@ -133,7 +134,6 @@ static const nir_shader_compiler_options nir_options = { static const nir_shader_compiler_options nir_options_a6xx = { COMMON_OPTIONS, .vectorize_io = true, - .max_unroll_iterations = 32, .force_indirect_unrolling = nir_var_all, .lower_wpos_pntc = true, .lower_cs_local_index_to_id = true, @@ -287,6 +287,9 @@ ir3_compiler_create(struct fd_device *dev, const struct fd_dev_id *dev_id, compiler->nir_options.has_sudot_4x8 = dev_info->a6xx.has_dp2acc; } else { compiler->nir_options = nir_options; + /* a2xx compiler doesn't handle indirect: */ + if (compiler->gen <= 2) + compiler->nir_options.force_indirect_unrolling = nir_var_all; } if (!options->disable_cache) diff --git a/src/gallium/drivers/freedreno/a2xx/ir2_nir.c b/src/gallium/drivers/freedreno/a2xx/ir2_nir.c index fc077c4372b..a36c1e4b777 100644 --- a/src/gallium/drivers/freedreno/a2xx/ir2_nir.c +++ b/src/gallium/drivers/freedreno/a2xx/ir2_nir.c @@ -51,6 +51,7 @@ static const nir_shader_compiler_options options = { .lower_insert_word = true, .force_indirect_unrolling = nir_var_all, .force_indirect_unrolling_sampler = true, + .max_unroll_iterations = 32, }; const nir_shader_compiler_options * diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index 68d1c59f293..cc1e0d4f7d6 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -649,6 +649,7 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: + case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: return 0; case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: return 1; @@ -675,8 +676,6 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen, COND(has_compute(screen) && (shader == PIPE_SHADER_COMPUTE), (1 << PIPE_SHADER_IR_NIR_SERIALIZED)) | (1 << PIPE_SHADER_IR_TGSI); - case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: - return 32; case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) {