anv: Fix shaders-lineno implementation for eu stall sampling

The implementation for dumping shader line numbers was broken for anv as of:
1de9f367e8 anv: remove unused gfx/compute pipeline code

Now the implementation is moved to the shader heap upload and mimics the
current implementation in iris.

Signed-off-by: Casey Bowman <casey.g.bowman@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40248>

src/intel/vulkan/anv_blorp.c

@@ -22,7 +22,6 @@
  */
 
 #include "anv_private.h"
-#include "compiler/brw/brw_disasm.h"
 #include "genxml/gen80_pack.h"
 
 static bool
@@ -86,15 +85,6 @@ upload_blorp_shader(struct blorp_batch *batch, uint32_t stage,
     */
    anv_shader_internal_unref(device, bin);
 
-   if (INTEL_DEBUG(DEBUG_SHADERS_LINENO)) {
-      /* shader hash is zero in this context */
-      if (!intel_shader_dump_filter) {
-         brw_disassemble_with_lineno(&device->physical->compiler->isa,
-                                     stage, -1, 0, kernel, 0,
-                                     bin->kernel.offset, stderr);
-      }
-   }
-
    *kernel_out = bin->kernel.offset;
    *(const struct brw_stage_prog_data **)prog_data_out = bin->prog_data;
 

src/intel/vulkan/anv_pipeline_cache.c

@@ -149,8 +149,11 @@ anv_shader_internal_create(struct anv_device *device,
       return NULL;
    }
 
-   anv_shader_heap_upload(&device->shader_heap, shader->kernel,
-                          kernel_data, kernel_size);
+   anv_shader_heap_upload(&device->shader_heap,
+                          shader->kernel,
+                          kernel_data,
+                          shader->prog_data,
+                          shader->stats->dispatch_width);
 
    return shader;
 }

src/intel/vulkan/anv_private.h

@@ -1300,7 +1300,9 @@ void anv_shader_heap_free(struct anv_shader_heap *heap, struct anv_shader_alloc
 
 void anv_shader_heap_upload(struct anv_shader_heap *heap,
                             struct anv_shader_alloc alloc,
-                            const void *data, uint64_t size);
+                            const void *data,
+                            const struct brw_stage_prog_data *prog_data,
+                            uint32_t dispatch_width);
 
 struct anv_shader_group_rt_replay {
    uint64_t general;

src/intel/vulkan/anv_shader.c

@@ -717,8 +717,10 @@ anv_shader_create(struct anv_device *device,
       goto error_state;
 
    anv_shader_heap_upload(&device->shader_heap,
-                          shader->kernel, shader_data->code,
-                          shader_data->prog_data.base.program_size);
+                          shader->kernel,
+                          shader_data->code,
+                          shader->prog_data,
+                          shader->stats->dispatch_width);
 
    if (mesa_shader_stage_is_rt(shader->vk.stage)) {
       const struct brw_bs_prog_data *bs_prog_data =
@@ -883,8 +885,10 @@ anv_replay_rt_shader_group(struct vk_device *vk_device,
          assert(result == VK_SUCCESS);
 
          anv_shader_heap_upload(&device->shader_heap,
-                                shader->replay_kernel, shader->code,
-                                shader->prog_data->program_size);
+                                shader->replay_kernel,
+                                shader->code,
+                                shader->prog_data,
+                                shader->stats->dispatch_width);
       }
 
       simple_mtx_unlock(&shader->replay_mutex);

src/intel/vulkan/anv_shader_heap.c

@@ -3,6 +3,7 @@
  */
 
 #include "anv_private.h"
+#include "compiler/brw/brw_disasm.h"
 
 static inline uint32_t
 shader_bo_index(struct anv_shader_heap *heap, uint64_t addr)
@@ -188,8 +189,11 @@ anv_shader_heap_free(struct anv_shader_heap *heap, struct anv_shader_alloc alloc
 void
 anv_shader_heap_upload(struct anv_shader_heap *heap,
                        struct anv_shader_alloc alloc,
-                       const void *data, uint64_t data_size)
+                       const void *data,
+                       const struct brw_stage_prog_data *prog_data,
+                       uint32_t dispatch_width)
 {
+   uint64_t data_size = prog_data->program_size;
    const uint32_t bo_begin_idx = shader_bo_index(
       heap, heap->va_range.addr + alloc.offset);
    const uint32_t bo_end_idx = shader_bo_index(
@@ -207,4 +211,19 @@ anv_shader_heap_upload(struct anv_shader_heap *heap,
 
       memcpy(heap->bos[i].bo->map + bo_offset, data, copy_size);
    }
+   if (INTEL_DEBUG(DEBUG_SHADERS_LINENO)) {
+      if (!intel_shader_dump_filter ||
+         (intel_shader_dump_filter && intel_shader_dump_filter == prog_data->source_hash)) {
+         int start = 0;
+         /* dump each simd variant of shader */
+         while (start < data_size) {
+            brw_disassemble_with_lineno(&heap->device->physical->compiler->isa,
+                                        prog_data->stage, -1,
+                                        prog_data->source_hash, data, start,
+                                        alloc.offset, stderr);
+            start += align64(brw_disassemble_find_end(&heap->device->physical->compiler->isa,
+                                                      data, start), 64);
+         }
+      }
+   }
 }