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anv: remove unused gfx/compute pipeline code

Browse source 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34872>
This commit is contained in:
Lionel Landwerlin 2025-04-07 14:20:05 +03:00 • committed by Marge Bot
parent e76ed91d3f
commit 1de9f367e8
11 changed files with 12 additions and 6930 deletions
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31
src/intel/vulkan/anv_cmd_buffer.c
View file

@ -497,37 +497,6 @@ anv_cmd_buffer_set_rt_query_buffer(struct anv_cmd_buffer *cmd_buffer,
pipeline_state->push_constants_data_dirty = true;
}
static enum anv_cmd_dirty_bits
get_pipeline_dirty_stages(struct anv_device *device,
struct anv_graphics_pipeline *old_pipeline,
struct anv_graphics_pipeline *new_pipeline)
{
if (!old_pipeline)
return ANV_CMD_DIRTY_ALL_SHADERS(device);
enum anv_cmd_dirty_bits bits = 0;
#define STAGE_CHANGED(_name) \
(old_pipeline->base.shaders[MESA_SHADER_##_name] != \
new_pipeline->base.shaders[MESA_SHADER_##_name])
if (STAGE_CHANGED(VERTEX))
bits |= ANV_CMD_DIRTY_VS;
if (STAGE_CHANGED(TESS_CTRL))
bits |= ANV_CMD_DIRTY_HS;
if (STAGE_CHANGED(TESS_EVAL))
bits |= ANV_CMD_DIRTY_DS;
if (STAGE_CHANGED(GEOMETRY))
bits |= ANV_CMD_DIRTY_GS;
if (STAGE_CHANGED(TASK))
bits |= ANV_CMD_DIRTY_TASK;
if (STAGE_CHANGED(MESH))
bits |= ANV_CMD_DIRTY_MESH;
if (STAGE_CHANGED(FRAGMENT))
bits |= ANV_CMD_DIRTY_PS;
#undef STAGE_CHANGED
return bits;
}
static void
update_push_descriptor_flags(struct anv_cmd_pipeline_state *state,
struct anv_shader ** const shaders,

127
src/intel/vulkan/anv_descriptor_set.c
View file

@ -1080,133 +1080,6 @@ void anv_DestroyDescriptorSetLayout(
vk_descriptor_set_layout_unref(&device->vk, &set_layout->vk);
}
void
anv_descriptor_set_layout_print(const struct anv_descriptor_set_layout *layout)
{
fprintf(stderr, "set layout:\n");
for (uint32_t b = 0; b < layout->binding_count; b++) {
fprintf(stderr, " binding%03u: offsets=0x%08x/0x%08x sizes=%04u/%04u strides=%03u/%03u planes=%hhu count=%03u\n",
b,
layout->binding[b].descriptor_surface_offset,
layout->binding[b].descriptor_sampler_offset,
layout->binding[b].descriptor_data_surface_size,
layout->binding[b].descriptor_data_sampler_size,
layout->binding[b].descriptor_surface_stride,
layout->binding[b].descriptor_sampler_stride,
layout->binding[b].max_plane_count,
layout->binding[b].array_size);
}
}
/*
* Pipeline layouts. These have nothing to do with the pipeline. They are
* just multiple descriptor set layouts pasted together
*/
void
anv_pipeline_sets_layout_init(struct anv_pipeline_sets_layout *layout,
struct anv_device *device,
bool independent_sets)
{
memset(layout, 0, sizeof(*layout));
layout->device = device;
layout->push_descriptor_set_index = -1;
layout->independent_sets = independent_sets;
}
void
anv_pipeline_sets_layout_add(struct anv_pipeline_sets_layout *layout,
uint32_t set_idx,
struct anv_descriptor_set_layout *set_layout)
{
if (layout->set_layouts[set_idx])
return;
/* Workaround CTS : Internal CTS issue 3584 */
if (layout->independent_sets && anv_descriptor_set_layout_empty(set_layout))
return;
if (layout->type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_UNKNOWN)
layout->type = set_layout->type;
else
assert(layout->type == set_layout->type);
layout->num_sets = MAX2(set_idx + 1, layout->num_sets);
layout->set_layouts[set_idx] = set_layout;
vk_descriptor_set_layout_ref(&set_layout->vk);
layout->dynamic_offset_start[set_idx] = layout->num_dynamic_buffers;
layout->num_dynamic_buffers += set_layout->vk.dynamic_descriptor_count;
assert(layout->num_dynamic_buffers < MAX_DYNAMIC_BUFFERS);
if (set_layout->vk.flags &
VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR) {
assert(layout->push_descriptor_set_index == -1);
layout->push_descriptor_set_index = set_idx;
}
}
uint32_t
anv_pipeline_sets_layout_embedded_sampler_count(const struct anv_pipeline_sets_layout *layout)
{
uint32_t count = 0;
for (unsigned s = 0; s < layout->num_sets; s++) {
if (!layout->set_layouts[s])
continue;
count += layout->set_layouts[s]->embedded_sampler_count;
}
return count;
}
void
anv_pipeline_sets_layout_hash(struct anv_pipeline_sets_layout *layout)
{
struct mesa_blake3 ctx;
_mesa_blake3_init(&ctx);
for (unsigned s = 0; s < layout->num_sets; s++) {
if (!layout->set_layouts[s])
continue;
_mesa_blake3_update(&ctx, &layout->set_layouts[s]->vk.blake3,
sizeof(layout->set_layouts[s]->vk.blake3));
_mesa_blake3_update(&ctx, &layout->dynamic_offset_start[s],
sizeof(layout->dynamic_offset_start[s]));
}
_mesa_blake3_update(&ctx, &layout->num_sets, sizeof(layout->num_sets));
_mesa_blake3_final(&ctx, layout->blake3);
}
void
anv_pipeline_sets_layout_fini(struct anv_pipeline_sets_layout *layout)
{
for (unsigned s = 0; s < layout->num_sets; s++) {
if (!layout->set_layouts[s])
continue;
vk_descriptor_set_layout_unref(&layout->device->vk,
&layout->set_layouts[s]->vk);
}
}
void
anv_pipeline_sets_layout_print(const struct anv_pipeline_sets_layout *layout)
{
fprintf(stderr, "layout: dyn_count=%u sets=%u ind=%u\n",
layout->num_dynamic_buffers,
layout->num_sets,
layout->independent_sets);
for (unsigned s = 0; s < layout->num_sets; s++) {
if (!layout->set_layouts[s])
continue;
fprintf(stderr, " set%i: dyn_start=%u flags=0x%x\n",
s, layout->dynamic_offset_start[s],
layout->set_layouts[s]->vk.flags);
}
}
/*
* Descriptor pools.
*

15
src/intel/vulkan/anv_genX.h
View file

@ -103,11 +103,6 @@ void genX(emit_pipeline_select)(struct anv_batch *batch, uint32_t pipeline,
void genX(apply_task_urb_workaround)(struct anv_cmd_buffer *cmd_buffer);
void genX(batch_emit_pipeline_vertex_input)(struct anv_batch *batch,
struct anv_device *device,
struct anv_graphics_pipeline *pipeline,
const struct vk_vertex_input_state *vi);
void genX(batch_emit_vertex_input)(struct anv_batch *batch,
struct anv_device *device,
struct anv_shader *shader,
@ -299,16 +294,6 @@ genX(batch_emit_post_3dprimitive_was)(struct anv_batch *batch,
void genX(batch_emit_fast_color_dummy_blit)(struct anv_batch *batch,
struct anv_device *device);
void
genX(graphics_pipeline_emit)(struct anv_graphics_pipeline *pipeline,
const struct vk_graphics_pipeline_state *state);
void
genX(compute_pipeline_emit)(struct anv_compute_pipeline *pipeline);
void
genX(ray_tracing_pipeline_emit)(struct anv_ray_tracing_pipeline *pipeline);
#if GFX_VERx10 >= 300
#define anv_shader_bin_get_handler(bin, local_arg_offset) ({ \
assert((local_arg_offset) % 8 == 0); \

6
src/intel/vulkan/anv_nir.h
View file

@ -68,9 +68,6 @@ struct anv_pipeline_push_map {
struct anv_pipeline_binding *block_to_descriptor;
};
enum brw_robustness_flags
anv_get_robust_flags(const struct vk_pipeline_robustness_state *rstate);
bool anv_check_for_primitive_replication(struct anv_device *device,
VkShaderStageFlags stages,
nir_shader **shaders,
@ -79,9 +76,6 @@ bool anv_check_for_primitive_replication(struct anv_device *device,
bool anv_nir_lower_multiview(nir_shader *shader, uint32_t view_mask,
bool use_primitive_replication);
bool anv_nir_lower_ycbcr_textures(nir_shader *shader,
const struct anv_pipeline_sets_layout *layout);
static inline nir_address_format
anv_nir_ssbo_addr_format(const struct anv_physical_device *pdevice,
enum brw_robustness_flags robust_flags)

4511
src/intel/vulkan/anv_pipeline.c
View file

File diff suppressed because it is too large Load diff

385
src/intel/vulkan/anv_private.h
View file

@ -1776,7 +1776,6 @@ struct anv_queue {
};
struct nir_xfb_info;
struct anv_pipeline_sets_layout;
struct anv_push_descriptor_info;
extern const struct vk_pipeline_cache_object_ops *const anv_cache_import_ops[2];
@ -3732,40 +3731,6 @@ anv_descriptor_set_write_template(struct anv_device *device,
const struct vk_descriptor_update_template *template,
const void *data);
struct anv_pipeline_sets_layout {
struct anv_device *device;
struct anv_descriptor_set_layout *set_layouts[MAX_SETS];
uint32_t dynamic_offset_start[MAX_SETS];
enum anv_descriptor_set_layout_type type;
uint32_t num_sets;
uint32_t num_dynamic_buffers;
int push_descriptor_set_index;
bool independent_sets;
blake3_hash blake3;
};
void anv_pipeline_sets_layout_init(struct anv_pipeline_sets_layout *layout,
struct anv_device *device,
bool independent_sets);
void anv_pipeline_sets_layout_fini(struct anv_pipeline_sets_layout *layout);
void anv_pipeline_sets_layout_add(struct anv_pipeline_sets_layout *layout,
uint32_t set_idx,
struct anv_descriptor_set_layout *set_layout);
uint32_t
anv_pipeline_sets_layout_embedded_sampler_count(const struct anv_pipeline_sets_layout *layout);
void anv_pipeline_sets_layout_hash(struct anv_pipeline_sets_layout *layout);
void anv_pipeline_sets_layout_print(const struct anv_pipeline_sets_layout *layout);
struct anv_sparse_binding_data {
uint64_t address;
uint64_t size;
@ -4402,11 +4367,6 @@ struct anv_cmd_pipeline_state {
* Push descriptor index for currently bound shaders (UINT8_MAX if unused).
*/
uint8_t push_descriptor_index;
/**
* The current bound pipeline.
*/
struct anv_pipeline *pipeline;
};
enum anv_depth_reg_mode {
@ -5230,331 +5190,11 @@ struct anv_pipeline_executable {
};
enum anv_pipeline_type {
ANV_PIPELINE_GRAPHICS,
ANV_PIPELINE_GRAPHICS_LIB,
ANV_PIPELINE_COMPUTE,
ANV_PIPELINE_RAY_TRACING,
};
void anv_shader_init_uuid(struct anv_physical_device *device);
struct anv_pipeline {
struct vk_pipeline vk;
struct anv_device * device;
struct anv_batch batch;
struct anv_reloc_list batch_relocs;
void * mem_ctx;
enum anv_pipeline_type type;
VkPipelineCreateFlags2KHR flags;
VkShaderStageFlags active_stages;
uint32_t ray_queries;
/**
* Mask of stages that are accessing push descriptors.
*/
VkShaderStageFlags use_push_descriptor;
/**
* Mask of stages that are accessing the push descriptors buffer.
*/
VkShaderStageFlags use_push_descriptor_buffer;
/**
* Maximum scratch size for all shaders in this pipeline.
*/
uint32_t scratch_size;
/* Layout of the sets used by the pipeline. */
struct anv_pipeline_sets_layout layout;
struct util_dynarray executables;
};
/* The base graphics pipeline object only hold shaders. */
struct anv_graphics_base_pipeline {
struct anv_pipeline base;
struct vk_sample_locations_state sample_locations;
/* Shaders */
struct anv_shader_bin * shaders[ANV_GRAPHICS_SHADER_STAGE_COUNT];
/* Feedback index in
* VkPipelineCreationFeedbackCreateInfo::pPipelineStageCreationFeedbacks
*
* For pipeline libraries, we need to remember the order at creation when
* included into a linked pipeline.
*/
uint32_t feedback_index[ANV_GRAPHICS_SHADER_STAGE_COUNT];
/* Robustness flags used shaders
*/
enum brw_robustness_flags robust_flags[ANV_GRAPHICS_SHADER_STAGE_COUNT];
};
/* The library graphics pipeline object has a partial graphic state and
* possibly some shaders. If requested, shaders are also present in NIR early
* form.
*/
struct anv_graphics_lib_pipeline {
struct anv_graphics_base_pipeline base;
VkGraphicsPipelineLibraryFlagsEXT lib_flags;
struct vk_graphics_pipeline_all_state all_state;
struct vk_graphics_pipeline_state state;
/* Retained shaders for link optimization. */
struct {
/* This hash is the same as computed in
* anv_graphics_pipeline_gather_shaders().
*/
unsigned char shader_sha1[20];
enum gl_subgroup_size subgroup_size_type;
/* Hold on the value of VK_PIPELINE_CREATE_VIEW_INDEX_FROM_DEVICE_INDEX_BIT
* from library that introduces the stage, so it remains consistent.
*/
bool view_index_from_device_index;
/* NIR captured in anv_pipeline_stage_get_nir(), includes specialization
* constants.
*/
nir_shader * nir;
} retained_shaders[ANV_GRAPHICS_SHADER_STAGE_COUNT];
/* Whether the shaders have been retained */
bool retain_shaders;
};
/* The final graphics pipeline object has all the graphics state ready to be
* programmed into HW packets (dynamic_state field) or fully baked in its
* batch.
*/
struct anv_graphics_pipeline {
struct anv_graphics_base_pipeline base;
uint32_t vs_source_hash;
uint32_t fs_source_hash;
struct vk_vertex_input_state vertex_input;
struct vk_sample_locations_state sample_locations;
struct vk_dynamic_graphics_state dynamic_state;
uint32_t view_mask;
uint32_t instance_multiplier;
bool kill_pixel;
bool uses_xfb;
/* Number of VERTEX_ELEMENT_STATE input elements used by the shader */
uint32_t vs_input_elements;
/* Number of VERTEX_ELEMENT_STATE elements we need to implement some of the
* draw parameters
*/
uint32_t svgs_count;
/* Pre computed VERTEX_ELEMENT_STATE structures for the vertex input that
* can be copied into the anv_cmd_buffer behind a 3DSTATE_VERTEX_BUFFER.
*
* When MESA_VK_DYNAMIC_VI is not dynamic
*
* vertex_input_elems = vs_input_elements + svgs_count
*
* All the VERTEX_ELEMENT_STATE can be directly copied behind a
* 3DSTATE_VERTEX_ELEMENTS instruction in the command buffer. Otherwise
* this array only holds the svgs_count elements.
*/
uint32_t vertex_input_elems;
uint32_t vertex_input_data[2 * 31 /* MAX_VES + 2 internal */];
/* Number of color outputs used by the fragment shader. */
uint8_t num_color_outputs;
/* Map of color output of the fragment shader to color attachments in the
* render pass.
*/
uint8_t color_output_mapping[MAX_RTS];
/* Pre computed CS instructions that can directly be copied into
* anv_cmd_buffer.
*/
uint32_t batch_data[480];
/* Urb setup utilized by this pipeline. */
struct intel_urb_config urb_cfg;
/* Fully backed instructions, ready to be emitted in the anv_cmd_buffer */
struct {
struct anv_gfx_state_ptr vf_sgvs;
struct anv_gfx_state_ptr vf_sgvs_2;
struct anv_gfx_state_ptr vf_sgvs_instancing;
struct anv_gfx_state_ptr vf_instancing;
struct anv_gfx_state_ptr vf_component_packing;
struct anv_gfx_state_ptr so_decl_list;
struct anv_gfx_state_ptr vs;
struct anv_gfx_state_ptr hs;
struct anv_gfx_state_ptr ds;
struct anv_gfx_state_ptr vs_protected;
struct anv_gfx_state_ptr hs_protected;
struct anv_gfx_state_ptr ds_protected;
struct anv_gfx_state_ptr task_control;
struct anv_gfx_state_ptr task_control_protected;
struct anv_gfx_state_ptr task_shader;
struct anv_gfx_state_ptr task_redistrib;
struct anv_gfx_state_ptr clip_mesh;
struct anv_gfx_state_ptr mesh_control;
struct anv_gfx_state_ptr mesh_control_protected;
struct anv_gfx_state_ptr mesh_shader;
struct anv_gfx_state_ptr mesh_distrib;
} final;
/* Pre packed CS instructions & structures that need to be merged later
* with dynamic state.
*/
struct {
struct anv_gfx_state_ptr ps_extra;
struct anv_gfx_state_ptr wm;
struct anv_gfx_state_ptr so;
struct anv_gfx_state_ptr gs;
struct anv_gfx_state_ptr gs_protected;
struct anv_gfx_state_ptr te;
struct anv_gfx_state_ptr ps;
struct anv_gfx_state_ptr ps_protected;
} partial;
};
#define anv_batch_emit_pipeline_state(batch, pipeline, state) \
do { \
if ((pipeline)->state.len == 0) \
break; \
uint32_t *dw; \
dw = anv_batch_emit_dwords((batch), (pipeline)->state.len); \
if (!dw) \
break; \
memcpy(dw, &(pipeline)->batch_data[(pipeline)->state.offset], \
4 * (pipeline)->state.len); \
} while (0)
#define anv_batch_emit_pipeline_state_protected(batch, pipeline, \
state, protected) \
do { \
struct anv_gfx_state_ptr *_cmd_state = protected ? \
&(pipeline)->state##_protected : &(pipeline)->state; \
if (_cmd_state->len == 0) \
break; \
uint32_t *dw; \
dw = anv_batch_emit_dwords((batch), _cmd_state->len); \
if (!dw) \
break; \
memcpy(dw, &(pipeline)->batch_data[_cmd_state->offset], \
4 * _cmd_state->len); \
} while (0)
struct anv_compute_pipeline {
struct anv_pipeline base;
struct anv_shader_bin * cs;
uint32_t batch_data[9];
union {
struct {
uint32_t interface_descriptor_data[8];
uint32_t gpgpu_walker[15];
} gfx9;
struct {
uint32_t compute_walker_body[39];
} gfx125;
};
};
struct anv_rt_shader_group {
VkRayTracingShaderGroupTypeKHR type;
/* Whether this group was imported from another pipeline */
bool imported;
struct anv_shader_bin *general;
struct anv_shader_bin *closest_hit;
struct anv_shader_bin *any_hit;
struct anv_shader_bin *intersection;
/* VK_KHR_ray_tracing requires shaderGroupHandleSize == 32 */
uint32_t handle[8];
};
struct anv_ray_tracing_pipeline {
struct anv_pipeline base;
/* All shaders in the pipeline */
struct util_dynarray shaders;
uint32_t group_count;
struct anv_rt_shader_group * groups;
/* If non-zero, this is the default computed stack size as per the stack
* size computation in the Vulkan spec. If zero, that indicates that the
* client has requested a dynamic stack size.
*/
uint32_t stack_size;
};
#define ANV_DECL_PIPELINE_DOWNCAST(pipe_type, pipe_enum) \
static inline struct anv_##pipe_type##_pipeline * \
anv_pipeline_to_##pipe_type(struct anv_pipeline *pipeline) \
{ \
assert(pipeline->type == pipe_enum); \
return (struct anv_##pipe_type##_pipeline *) pipeline; \
}
ANV_DECL_PIPELINE_DOWNCAST(graphics, ANV_PIPELINE_GRAPHICS)
ANV_DECL_PIPELINE_DOWNCAST(graphics_lib, ANV_PIPELINE_GRAPHICS_LIB)
ANV_DECL_PIPELINE_DOWNCAST(compute, ANV_PIPELINE_COMPUTE)
ANV_DECL_PIPELINE_DOWNCAST(ray_tracing, ANV_PIPELINE_RAY_TRACING)
/* Can't use the macro because we need to handle both types. */
static inline struct anv_graphics_base_pipeline *
anv_pipeline_to_graphics_base(struct anv_pipeline *pipeline)
{
assert(pipeline->type == ANV_PIPELINE_GRAPHICS ||
pipeline->type == ANV_PIPELINE_GRAPHICS_LIB);
return (struct anv_graphics_base_pipeline *) pipeline;
}
static inline bool
anv_pipeline_has_stage(const struct anv_graphics_pipeline *pipeline,
mesa_shader_stage stage)
{
return (pipeline->base.base.active_stages & mesa_to_vk_shader_stage(stage)) != 0;
}
static inline bool
anv_pipeline_base_has_stage(const struct anv_graphics_base_pipeline *pipeline,
mesa_shader_stage stage)
{
return (pipeline->base.active_stages & mesa_to_vk_shader_stage(stage)) != 0;
}
static inline bool
anv_pipeline_is_primitive(const struct anv_graphics_pipeline *pipeline)
{
return anv_pipeline_has_stage(pipeline, MESA_SHADER_VERTEX);
}
static inline bool
anv_pipeline_is_mesh(const struct anv_graphics_pipeline *pipeline)
{
return anv_pipeline_has_stage(pipeline, MESA_SHADER_MESH);
}
static inline bool
anv_gfx_has_stage(const struct anv_cmd_graphics_state *gfx,
mesa_shader_stage stage)
@ -5595,18 +5235,6 @@ anv_cmd_graphic_state_update_has_uint_rt(struct anv_cmd_graphics_state *state)
#define ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(prefix, stage) \
static inline const struct brw_##prefix##_prog_data * \
get_pipeline_##prefix##_prog_data( \
const struct anv_graphics_pipeline *pipeline) \
{ \
if (anv_pipeline_has_stage(pipeline, stage)) { \
return (const struct brw_##prefix##_prog_data *) \
pipeline->base.shaders[stage]->prog_data; \
} else { \
return NULL; \
} \
} \
\
static inline const struct brw_##prefix##_prog_data * \
get_gfx_##prefix##_prog_data( \
const struct anv_cmd_graphics_state *gfx) \
{ \
@ -5668,17 +5296,6 @@ get_shader_cs_prog_data(const struct anv_shader *shader)
return (const struct brw_cs_prog_data *) shader->prog_data;
}
static inline const struct brw_vue_prog_data *
anv_pipeline_get_last_vue_prog_data(const struct anv_graphics_pipeline *pipeline)
{
if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
return &get_pipeline_gs_prog_data(pipeline)->base;
else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
return &get_pipeline_tes_prog_data(pipeline)->base;
else
return &get_pipeline_vs_prog_data(pipeline)->base;
}
VkResult
anv_device_init_rt_shaders(struct anv_device *device);
@ -7177,8 +6794,6 @@ VK_DEFINE_NONDISP_HANDLE_CASTS(anv_event, base, VkEvent, VK_OBJECT_TYPE_EVENT)
VK_DEFINE_NONDISP_HANDLE_CASTS(anv_image, vk.base, VkImage, VK_OBJECT_TYPE_IMAGE)
VK_DEFINE_NONDISP_HANDLE_CASTS(anv_image_view, vk.base, VkImageView,
VK_OBJECT_TYPE_IMAGE_VIEW);
VK_DEFINE_NONDISP_HANDLE_CASTS(anv_pipeline, vk.base, VkPipeline,
VK_OBJECT_TYPE_PIPELINE)
VK_DEFINE_NONDISP_HANDLE_CASTS(anv_query_pool, vk.base, VkQueryPool,
VK_OBJECT_TYPE_QUERY_POOL)
VK_DEFINE_NONDISP_HANDLE_CASTS(anv_sampler, vk.base, VkSampler,

107
src/intel/vulkan/anv_rmv.c
View file

@ -720,113 +720,6 @@ anv_rmv_log_descriptor_pool_create(struct anv_device *device,
}
}
void
anv_rmv_log_graphics_pipeline_create(struct anv_device *device,
struct anv_graphics_pipeline *pipeline,
bool is_internal)
{
struct vk_rmv_resource_create_token create_token = {
.type = VK_RMV_RESOURCE_TYPE_PIPELINE,
.resource_id = resource_id_locked(device, pipeline),
.is_driver_internal = is_internal,
.pipeline = {
.is_internal = is_internal,
.hash_lo = 0,/* TODO pipeline->pipeline_hash; */
.shader_stages = pipeline->base.base.active_stages,
},
};
simple_mtx_lock(&device->vk.memory_trace_data.token_mtx);
vk_rmv_emit_token(&device->vk.memory_trace_data, VK_RMV_TOKEN_TYPE_RESOURCE_CREATE, &create_token);
for (unsigned s = 0; s < ARRAY_SIZE(pipeline->base.shaders); s++) {
struct anv_shader_bin *shader = pipeline->base.shaders[s];
if (!shader)
continue;
log_state_pool_bind_locked(device, create_token.resource_id,
&device->instruction_state_pool,
&shader->kernel);
}
simple_mtx_unlock(&device->vk.memory_trace_data.token_mtx);
}
void
anv_rmv_log_compute_pipeline_create(struct anv_device *device,
struct anv_compute_pipeline *pipeline,
bool is_internal)
{
VkShaderStageFlagBits active_stages =
pipeline->base.type == ANV_PIPELINE_COMPUTE ?
VK_SHADER_STAGE_COMPUTE_BIT : VK_SHADER_STAGE_RAYGEN_BIT_KHR;
simple_mtx_lock(&device->vk.memory_trace_data.token_mtx);
struct vk_rmv_resource_create_token create_token = {
.type = VK_RMV_RESOURCE_TYPE_PIPELINE,
.resource_id = resource_id_locked(device, pipeline),
.is_driver_internal = is_internal,
.pipeline = {
.is_internal = is_internal,
.hash_lo = 0,/* TODO pipeline->pipeline_hash; */
.shader_stages = active_stages,
},
};
vk_rmv_emit_token(&device->vk.memory_trace_data, VK_RMV_TOKEN_TYPE_RESOURCE_CREATE, &create_token);
struct anv_shader_bin *shader = pipeline->cs;
log_state_pool_bind_locked(device, create_token.resource_id,
&device->instruction_state_pool,
&shader->kernel);
simple_mtx_unlock(&device->vk.memory_trace_data.token_mtx);
}
void
anv_rmv_log_rt_pipeline_create(struct anv_device *device,
struct anv_ray_tracing_pipeline *pipeline,
bool is_internal)
{
simple_mtx_lock(&device->vk.memory_trace_data.token_mtx);
struct vk_rmv_resource_create_token create_token = {
.resource_id = resource_id_locked(device, pipeline),
.type = VK_RMV_RESOURCE_TYPE_PIPELINE,
.is_driver_internal = is_internal,
.pipeline = {
.is_internal = is_internal,
.hash_lo = 0, /* TODO */
.shader_stages = pipeline->base.active_stages,
},
};
vk_rmv_emit_token(&device->vk.memory_trace_data, VK_RMV_TOKEN_TYPE_RESOURCE_CREATE, &create_token);
struct anv_state_pool *state_pool = &device->instruction_state_pool;
for (uint32_t i = 0; i < pipeline->group_count; i++) {
struct anv_rt_shader_group *group = &pipeline->groups[i];
if (group->imported)
continue;
if (group->general) {
log_state_pool_bind_locked(device, create_token.resource_id, state_pool,
&group->general->kernel);
}
if (group->closest_hit) {
log_state_pool_bind_locked(device, create_token.resource_id, state_pool,
&group->closest_hit->kernel);
}
if (group->any_hit) {
log_state_pool_bind_locked(device, create_token.resource_id, state_pool,
&group->any_hit->kernel);
}
if (group->intersection) {
log_state_pool_bind_locked(device, create_token.resource_id, state_pool,
&group->intersection->kernel);
}
}
simple_mtx_unlock(&device->vk.memory_trace_data.token_mtx);
}
void
anv_rmv_log_event_create(struct anv_device *device,
struct anv_event *event,

12
src/intel/vulkan/anv_rmv.h
View file

@ -37,9 +37,6 @@ struct anv_buffer;
struct anv_image;
struct anv_bo;
struct anv_event;
struct anv_graphics_pipeline;
struct anv_compute_pipeline;
struct anv_ray_tracing_pipeline;
enum anv_image_memory_binding;
@ -101,15 +98,6 @@ void anv_rmv_log_descriptor_pool_create(struct anv_device *device,
const VkDescriptorPoolCreateInfo *create_info,
struct anv_descriptor_pool *pool,
bool is_internal);
void anv_rmv_log_graphics_pipeline_create(struct anv_device *device,
struct anv_graphics_pipeline *pipeline,
bool is_internal);
void anv_rmv_log_compute_pipeline_create(struct anv_device *device,
struct anv_compute_pipeline *pipeline,
bool is_internal);
void anv_rmv_log_rt_pipeline_create(struct anv_device *device,
struct anv_ray_tracing_pipeline *pipeline,
bool is_internal);
void anv_rmv_log_event_create(struct anv_device *device,
struct anv_event *event,
VkEventCreateFlags flags, bool is_internal);

12
src/intel/vulkan/anv_shader_compile.c
View file

@ -16,6 +16,18 @@
#include "compiler/brw_nir_rt.h"
#include "compiler/intel_nir.h"
static enum brw_robustness_flags
anv_get_robust_flags(const struct vk_pipeline_robustness_state *rstate)
{
return
((rstate->storage_buffers !=
VK_PIPELINE_ROBUSTNESS_BUFFER_BEHAVIOR_DISABLED_EXT) ?
BRW_ROBUSTNESS_SSBO : 0) |
((rstate->uniform_buffers !=
VK_PIPELINE_ROBUSTNESS_BUFFER_BEHAVIOR_DISABLED_EXT) ?
BRW_ROBUSTNESS_UBO : 0);
}
static enum anv_descriptor_set_layout_type
set_layouts_get_layout_type(struct anv_descriptor_set_layout * const *set_layouts,
uint32_t set_layout_count)

1734
src/intel/vulkan/genX_pipeline.c
View file

File diff suppressed because it is too large Load diff

2
src/intel/vulkan/meson.build
View file

@ -96,7 +96,6 @@ anv_per_hw_ver_files = files(
'genX_gpu_memcpy.c',
'genX_init_state.c',
'genX_internal_kernels.c',
'genX_pipeline.c',
'genX_query.c',
'genX_simple_shader.c',
'genX_shader.c',
@ -181,7 +180,6 @@ libanv_files = files(
'anv_nir_push_descriptor_analysis.c',
'anv_perf.c',
'anv_physical_device.c',
'anv_pipeline.c',
'anv_pipeline_cache.c',
'anv_private.h',
'anv_queue.c',