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anv/nir: Unify inputs_read/outputs_written between geometry stages

Browse source 
inputs_read/outputs_written are used for a shader stage to
determine the layout of input and output storage. Adjacent stages must
agree on the layout, so adjacent input/output bitfields must match.

Most of the time, cross-stage optimizations make that happen anyway,
but there are some cases (with special values like clip distances and
point size) where this doesn't happen.

Fixes crashes in dEQP-VK.subgroups.*.framebuffer.*_tess_eval

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3210
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6102>
(cherry picked from commit 2701f887fc)
This commit is contained in:
Danylo Piliaiev 2020-07-27 18:00:41 +03:00 • committed by Dylan Baker
parent a4dc1baf77
commit 55ef5d5a22
2 changed files with 28 additions and 3 deletions
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2
.pick_status.json
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@ -22,7 +22,7 @@
"description": "anv/nir: Unify inputs_read/outputs_written between geometry stages",
"nominated": true,
"nomination_type": 0,
"resolution": 0,
"resolution": 1,
"master_sha": null,
"because_sha": null
},

29
src/intel/vulkan/anv_pipeline.c
View file

@ -1505,14 +1505,39 @@ anv_pipeline_compile_graphics(struct anv_graphics_pipeline *pipeline,
void *stage_ctx = ralloc_context(NULL);
anv_pipeline_lower_nir(&pipeline->base, stage_ctx, &stages[s], layout);
if (prev_stage && compiler->glsl_compiler_options[s].NirOptions->unify_interfaces) {
prev_stage->nir->info.outputs_written |= stages[s].nir->info.inputs_read &
~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
stages[s].nir->info.inputs_read |= prev_stage->nir->info.outputs_written &
~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
prev_stage->nir->info.patch_outputs_written |= stages[s].nir->info.patch_inputs_read;
stages[s].nir->info.patch_inputs_read |= prev_stage->nir->info.patch_outputs_written;
}
ralloc_free(stage_ctx);
stages[s].feedback.duration += os_time_get_nano() - stage_start;
prev_stage = &stages[s];
}
prev_stage = NULL;
for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
if (!stages[s].entrypoint)
continue;
int64_t stage_start = os_time_get_nano();
void *stage_ctx = ralloc_context(NULL);
nir_xfb_info *xfb_info = NULL;
if (s == MESA_SHADER_VERTEX ||
s == MESA_SHADER_TESS_EVAL ||
s == MESA_SHADER_GEOMETRY)
xfb_info = nir_gather_xfb_info(stages[s].nir, stage_ctx);
anv_pipeline_lower_nir(&pipeline->base, stage_ctx, &stages[s], layout);
switch (s) {
case MESA_SHADER_VERTEX:
anv_pipeline_compile_vs(compiler, stage_ctx, pipeline,