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https://gitlab.freedesktop.org/mesa/mesa.git
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asahi,hk: factor out zls_control pack helper
makes both drivers a lot more readable, but especially gl Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34585>
This commit is contained in:
Alyssa Rosenzweig
Marge Bot
parent
3a560dd32b
commit
551355d4e5
3 changed files with 152 additions and 155 deletions
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@ -106,6 +106,41 @@ agx_translate_zls_tiling(enum ail_tiling tiling)
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}
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}
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struct agx_zls {
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bool z_load, z_store;
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bool s_load, s_store;
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};
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static inline void
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agx_pack_zls_control(struct agx_zls_control_packed *packed,
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const struct ail_layout *z, const struct ail_layout *s,
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struct agx_zls *args)
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{
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agx_pack(packed, ZLS_CONTROL, cfg) {
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if (z) {
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cfg.z_store_enable = args->z_store;
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cfg.z_load_enable = args->z_load;
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cfg.z_load_compress = cfg.z_store_compress = z->compressed;
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cfg.z_load_tiling = cfg.z_store_tiling =
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agx_translate_zls_tiling(z->tiling);
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if (z->format == PIPE_FORMAT_Z16_UNORM) {
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cfg.z_format = AGX_ZLS_FORMAT_16;
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} else {
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cfg.z_format = AGX_ZLS_FORMAT_32F;
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}
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}
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if (s) {
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cfg.s_load_enable = args->s_load;
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cfg.s_store_enable = args->s_store;
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cfg.s_load_compress = cfg.s_store_compress = s->compressed;
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cfg.s_load_tiling = cfg.s_store_tiling =
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agx_translate_zls_tiling(s->tiling);
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}
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}
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}
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static enum agx_sample_count
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agx_translate_sample_count(unsigned samples)
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{
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@ -521,61 +521,41 @@ hk_merge_render_iview(struct hk_rendering_state *render,
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static void
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hk_pack_zls_control(struct agx_zls_control_packed *packed,
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struct ail_layout *z_layout, struct ail_layout *s_layout,
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const VkRenderingAttachmentInfo *attach_z,
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const VkRenderingAttachmentInfo *attach_s,
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const VkRenderingAttachmentInfo *z,
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const VkRenderingAttachmentInfo *s,
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bool incomplete_render_area, bool partial_render)
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{
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agx_pack(packed, ZLS_CONTROL, zls_control) {
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if (z_layout) {
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/* XXX: Dropping Z stores is wrong if the render pass gets split into
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* multiple control streams (can that ever happen?) We need more ZLS
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* variants. Force || true for now.
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*/
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zls_control.z_store_enable =
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attach_z->storeOp == VK_ATTACHMENT_STORE_OP_STORE ||
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attach_z->resolveMode != VK_RESOLVE_MODE_NONE || partial_render ||
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true;
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struct agx_zls zls = {0};
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zls_control.z_load_enable =
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attach_z->loadOp == VK_ATTACHMENT_LOAD_OP_LOAD || partial_render ||
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incomplete_render_area;
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if (z) {
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/* XXX: Dropping Z stores is wrong if the render pass gets split into
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* multiple control streams (can that ever happen?) We need more ZLS
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* variants. Force || true for now.
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*/
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zls.z_store = z->storeOp == VK_ATTACHMENT_STORE_OP_STORE ||
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z->resolveMode != VK_RESOLVE_MODE_NONE || partial_render ||
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true;
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zls_control.z_load_tiling = zls_control.z_store_tiling =
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agx_translate_zls_tiling(z_layout->tiling);
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zls_control.z_load_compress = zls_control.z_store_compress =
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z_layout->compressed;
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if (z_layout->format == PIPE_FORMAT_Z16_UNORM) {
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zls_control.z_format = AGX_ZLS_FORMAT_16;
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} else {
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zls_control.z_format = AGX_ZLS_FORMAT_32F;
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}
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}
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if (s_layout) {
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/* TODO:
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* Fail
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* dEQP-VK.renderpass.dedicated_allocation.formats.d32_sfloat_s8_uint.input.dont_care.store.self_dep_clear_draw_use_input_aspect
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* without the force
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* .. maybe a VkRenderPass emulation bug.
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*/
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zls_control.s_store_enable =
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attach_s->storeOp == VK_ATTACHMENT_STORE_OP_STORE ||
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attach_s->resolveMode != VK_RESOLVE_MODE_NONE || partial_render ||
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true;
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zls_control.s_load_enable =
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attach_s->loadOp == VK_ATTACHMENT_LOAD_OP_LOAD || partial_render ||
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incomplete_render_area;
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zls_control.s_load_tiling = zls_control.s_store_tiling =
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agx_translate_zls_tiling(s_layout->tiling);
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zls_control.s_load_compress = zls_control.s_store_compress =
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s_layout->compressed;
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}
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zls.z_load = z->loadOp == VK_ATTACHMENT_LOAD_OP_LOAD || partial_render ||
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incomplete_render_area;
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}
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if (s) {
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/* TODO:
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* Fail
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* dEQP-VK.renderpass.dedicated_allocation.formats.d32_sfloat_s8_uint.input.dont_care.store.self_dep_clear_draw_use_input_aspect
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* without the force
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* .. maybe a VkRenderPass emulation bug.
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*/
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zls.s_store = s->storeOp == VK_ATTACHMENT_STORE_OP_STORE ||
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s->resolveMode != VK_RESOLVE_MODE_NONE || partial_render ||
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true;
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zls.s_load = s->loadOp == VK_ATTACHMENT_LOAD_OP_LOAD || partial_render ||
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incomplete_render_area;
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}
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agx_pack_zls_control(packed, z_layout, s_layout, &zls);
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}
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VKAPI_ATTR void VKAPI_CALL
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@ -1241,6 +1241,7 @@ agx_cmdbuf(struct agx_device *dev, struct drm_asahi_cmd_render *c,
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c->isp_bgobjvals = 0x300;
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struct agx_resource *zres = NULL, *sres = NULL;
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struct pipe_surface *zsbuf = framebuffer->zsbuf;
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if (framebuffer->zsbuf) {
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agx_pack(&c->isp_zls_pixels, CR_ISP_ZLS_PIXELS, cfg) {
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@ -1249,127 +1250,108 @@ agx_cmdbuf(struct agx_device *dev, struct drm_asahi_cmd_render *c,
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}
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}
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agx_pack(&c->zls_ctrl, ZLS_CONTROL, zls_control) {
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if (zsbuf) {
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struct agx_resource *zsres = agx_resource(zsbuf->texture);
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const struct util_format_description *desc =
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util_format_description(zsres->layout.format);
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if (framebuffer->zsbuf) {
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struct pipe_surface *zsbuf = framebuffer->zsbuf;
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struct agx_resource *zsres = agx_resource(zsbuf->texture);
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assert(desc->format == PIPE_FORMAT_Z32_FLOAT ||
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desc->format == PIPE_FORMAT_Z16_UNORM ||
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desc->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT ||
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desc->format == PIPE_FORMAT_S8_UINT);
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unsigned level = zsbuf->u.tex.level;
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unsigned first_layer = zsbuf->u.tex.first_layer;
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if (util_format_has_depth(desc))
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zres = zsres;
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else
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sres = zsres;
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const struct util_format_description *desc = util_format_description(
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agx_resource(zsbuf->texture)->layout.format);
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if (zsres->separate_stencil)
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sres = zsres->separate_stencil;
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assert(desc->format == PIPE_FORMAT_Z32_FLOAT ||
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desc->format == PIPE_FORMAT_Z16_UNORM ||
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desc->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT ||
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desc->format == PIPE_FORMAT_S8_UINT);
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unsigned level = zsbuf->u.tex.level;
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unsigned first_layer = zsbuf->u.tex.first_layer;
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if (util_format_has_depth(desc))
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zres = zsres;
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else
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sres = zsres;
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if (zres) {
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c->depth.base = agx_map_texture_gpu(zres, first_layer) +
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ail_get_level_offset_B(&zres->layout, level);
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if (zsres->separate_stencil)
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sres = zsres->separate_stencil;
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/* Main stride in pages */
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assert((zres->layout.depth_px == 1 ||
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is_aligned(zres->layout.layer_stride_B, AIL_PAGESIZE)) &&
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"Page aligned Z layers");
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if (zres) {
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bool clear = (batch->clear & PIPE_CLEAR_DEPTH);
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bool load = (batch->load & PIPE_CLEAR_DEPTH);
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unsigned stride_pages = zres->layout.layer_stride_B / AIL_PAGESIZE;
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c->depth.stride = ((stride_pages - 1) << 14) | 1;
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zls_control.z_store_enable = (batch->resolve & PIPE_CLEAR_DEPTH);
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zls_control.z_load_enable = !clear && load;
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if (zres->layout.compressed) {
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c->depth.comp_base =
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agx_map_texture_gpu(zres, 0) + zres->layout.metadata_offset_B +
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(first_layer * zres->layout.compression_layer_stride_B) +
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zres->layout.level_offsets_compressed_B[level];
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zls_control.z_load_tiling = zls_control.z_store_tiling =
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agx_translate_zls_tiling(zres->layout.tiling);
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zls_control.z_load_compress = zls_control.z_store_compress =
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zres->layout.compressed;
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c->depth.base = agx_map_texture_gpu(zres, first_layer) +
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ail_get_level_offset_B(&zres->layout, level);
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/* Main stride in pages */
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assert((zres->layout.depth_px == 1 ||
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is_aligned(zres->layout.layer_stride_B, AIL_PAGESIZE)) &&
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"Page aligned Z layers");
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unsigned stride_pages = zres->layout.layer_stride_B / AIL_PAGESIZE;
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c->depth.stride = ((stride_pages - 1) << 14) | 1;
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if (zres->layout.compressed) {
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c->depth.comp_base =
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agx_map_texture_gpu(zres, 0) +
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zres->layout.metadata_offset_B +
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(first_layer * zres->layout.compression_layer_stride_B) +
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zres->layout.level_offsets_compressed_B[level];
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/* Meta stride in cache lines */
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assert(is_aligned(zres->layout.compression_layer_stride_B,
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AIL_CACHELINE) &&
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"Cacheline aligned Z meta layers");
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unsigned stride_lines =
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zres->layout.compression_layer_stride_B / AIL_CACHELINE;
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c->depth.comp_stride = (stride_lines - 1) << 14;
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}
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if (zres->base.format == PIPE_FORMAT_Z16_UNORM) {
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const float scale = 0xffff;
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c->isp_bgobjdepth =
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(uint16_t)(SATURATE(clear_depth) * scale + 0.5f);
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zls_control.z_format = AGX_ZLS_FORMAT_16;
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c->flags |= DRM_ASAHI_RENDER_DBIAS_IS_INT;
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} else {
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c->isp_bgobjdepth = fui(clear_depth);
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zls_control.z_format = AGX_ZLS_FORMAT_32F;
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}
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/* Meta stride in cache lines */
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assert(is_aligned(zres->layout.compression_layer_stride_B,
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AIL_CACHELINE) &&
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"Cacheline aligned Z meta layers");
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unsigned stride_lines =
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zres->layout.compression_layer_stride_B / AIL_CACHELINE;
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c->depth.comp_stride = (stride_lines - 1) << 14;
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}
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if (sres) {
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bool clear = (batch->clear & PIPE_CLEAR_STENCIL);
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bool load = (batch->load & PIPE_CLEAR_STENCIL);
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if (zres->base.format == PIPE_FORMAT_Z16_UNORM) {
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const float scale = 0xffff;
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c->isp_bgobjdepth =
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(uint16_t)(SATURATE(clear_depth) * scale + 0.5f);
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zls_control.s_store_enable = (batch->resolve & PIPE_CLEAR_STENCIL);
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zls_control.s_load_enable = !clear && load;
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zls_control.s_load_tiling = zls_control.s_store_tiling =
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agx_translate_zls_tiling(sres->layout.tiling);
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zls_control.s_load_compress = zls_control.s_store_compress =
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sres->layout.compressed;
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c->stencil.base = agx_map_texture_gpu(sres, first_layer) +
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ail_get_level_offset_B(&sres->layout, level);
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/* Main stride in pages */
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assert((sres->layout.depth_px == 1 ||
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is_aligned(sres->layout.layer_stride_B, AIL_PAGESIZE)) &&
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"Page aligned S layers");
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unsigned stride_pages = sres->layout.layer_stride_B / AIL_PAGESIZE;
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c->stencil.stride = ((stride_pages - 1) << 14) | 1;
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if (sres->layout.compressed) {
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c->stencil.comp_base =
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agx_map_texture_gpu(sres, 0) +
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sres->layout.metadata_offset_B +
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(first_layer * sres->layout.compression_layer_stride_B) +
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sres->layout.level_offsets_compressed_B[level];
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/* Meta stride in cache lines */
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assert(is_aligned(sres->layout.compression_layer_stride_B,
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AIL_CACHELINE) &&
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"Cacheline aligned S meta layers");
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unsigned stride_lines =
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sres->layout.compression_layer_stride_B / AIL_CACHELINE;
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c->stencil.comp_stride = (stride_lines - 1) << 14;
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}
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c->isp_bgobjvals |= clear_stencil;
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c->flags |= DRM_ASAHI_RENDER_DBIAS_IS_INT;
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} else {
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c->isp_bgobjdepth = fui(clear_depth);
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}
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}
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if (sres) {
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c->stencil.base = agx_map_texture_gpu(sres, first_layer) +
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ail_get_level_offset_B(&sres->layout, level);
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/* Main stride in pages */
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assert((sres->layout.depth_px == 1 ||
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is_aligned(sres->layout.layer_stride_B, AIL_PAGESIZE)) &&
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"Page aligned S layers");
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unsigned stride_pages = sres->layout.layer_stride_B / AIL_PAGESIZE;
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c->stencil.stride = ((stride_pages - 1) << 14) | 1;
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if (sres->layout.compressed) {
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c->stencil.comp_base =
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agx_map_texture_gpu(sres, 0) + sres->layout.metadata_offset_B +
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(first_layer * sres->layout.compression_layer_stride_B) +
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sres->layout.level_offsets_compressed_B[level];
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/* Meta stride in cache lines */
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assert(is_aligned(sres->layout.compression_layer_stride_B,
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AIL_CACHELINE) &&
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"Cacheline aligned S meta layers");
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unsigned stride_lines =
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sres->layout.compression_layer_stride_B / AIL_CACHELINE;
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c->stencil.comp_stride = (stride_lines - 1) << 14;
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}
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c->isp_bgobjvals |= clear_stencil;
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}
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}
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unsigned load = batch->load & ~batch->clear;
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struct agx_zls zls = {
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.z_store = batch->resolve & PIPE_CLEAR_DEPTH,
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.s_store = batch->resolve & PIPE_CLEAR_STENCIL,
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.z_load = load & PIPE_CLEAR_DEPTH,
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.s_load = load & PIPE_CLEAR_STENCIL,
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};
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agx_pack_zls_control((struct agx_zls_control_packed *)&c->zls_ctrl,
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zres ? &zres->layout : NULL,
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sres ? &sres->layout : NULL, &zls);
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if (dev->debug & AGX_DBG_NOCLUSTER)
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c->flags |= DRM_ASAHI_RENDER_NO_VERTEX_CLUSTERING;
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