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asahi: identify ZLS compress load/store bits
obvious in retrospect! Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34585>
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3 changed files with 16 additions and 18 deletions
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@ -1108,13 +1108,13 @@
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<struct name="ZLS Control" size="8">
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<field name="Unknown 0" start="0" size="1" type="bool"/>
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<field name="Z Load Tiling" start="1" size="1" type="ZLS Tiling"/>
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<field name="Z Compress 1" start="2" size="1" type="bool"/>
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<field name="Z Load Compress" start="2" size="1" type="bool"/>
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<field name="S Load Tiling" start="3" size="1" type="ZLS Tiling"/>
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<field name="S Compress 1" start="4" size="1" type="bool"/>
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<field name="S Load Compress" start="4" size="1" type="bool"/>
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<field name="Z Store Tiling" start="5" size="1" type="ZLS Tiling"/>
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<field name="Z Compress 2" start="6" size="1" type="bool"/>
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<field name="Z Store Compress" start="6" size="1" type="bool"/>
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<field name="S Store Tiling" start="7" size="1" type="ZLS Tiling"/>
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<field name="S Compress 2" start="8" size="1" type="bool"/>
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<field name="S Store Compress" start="8" size="1" type="bool"/>
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<field name="S Load Enable" start="14" size="1" type="bool"/>
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<field name="Z Load Enable" start="15" size="1" type="bool"/>
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<field name="S Store Enable" start="18" size="1" type="bool"/>
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@ -543,10 +543,8 @@ hk_pack_zls_control(struct agx_zls_control_packed *packed,
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zls_control.z_load_tiling = zls_control.z_store_tiling =
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agx_translate_zls_tiling(z_layout->tiling);
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if (z_layout->compressed) {
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zls_control.z_compress_1 = true;
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zls_control.z_compress_2 = true;
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}
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zls_control.z_load_compress = zls_control.z_store_compress =
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z_layout->compressed;
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if (z_layout->format == PIPE_FORMAT_Z16_UNORM) {
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zls_control.z_format = AGX_ZLS_FORMAT_16;
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@ -574,10 +572,8 @@ hk_pack_zls_control(struct agx_zls_control_packed *packed,
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zls_control.s_load_tiling = zls_control.s_store_tiling =
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agx_translate_zls_tiling(s_layout->tiling);
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if (s_layout->compressed) {
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zls_control.s_compress_1 = true;
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zls_control.s_compress_2 = true;
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}
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zls_control.s_load_compress = zls_control.s_store_compress =
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s_layout->compressed;
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}
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}
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}
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@ -1280,9 +1280,13 @@ agx_cmdbuf(struct agx_device *dev, struct drm_asahi_cmd_render *c,
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zls_control.z_store_enable = (batch->resolve & PIPE_CLEAR_DEPTH);
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zls_control.z_load_enable = !clear && load;
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zls_control.z_load_tiling = zls_control.z_store_tiling =
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agx_translate_zls_tiling(zres->layout.tiling);
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zls_control.z_load_compress = zls_control.z_store_compress =
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zres->layout.compressed;
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c->depth.base = agx_map_texture_gpu(zres, first_layer) +
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ail_get_level_offset_B(&zres->layout, level);
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@ -1308,9 +1312,6 @@ agx_cmdbuf(struct agx_device *dev, struct drm_asahi_cmd_render *c,
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unsigned stride_lines =
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zres->layout.compression_layer_stride_B / AIL_CACHELINE;
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c->depth.comp_stride = (stride_lines - 1) << 14;
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zls_control.z_compress_1 = true;
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zls_control.z_compress_2 = true;
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}
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if (zres->base.format == PIPE_FORMAT_Z16_UNORM) {
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@ -1331,9 +1332,13 @@ agx_cmdbuf(struct agx_device *dev, struct drm_asahi_cmd_render *c,
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zls_control.s_store_enable = (batch->resolve & PIPE_CLEAR_STENCIL);
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zls_control.s_load_enable = !clear && load;
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zls_control.s_load_tiling = zls_control.s_store_tiling =
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agx_translate_zls_tiling(sres->layout.tiling);
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zls_control.s_load_compress = zls_control.s_store_compress =
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sres->layout.compressed;
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c->stencil.base = agx_map_texture_gpu(sres, first_layer) +
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ail_get_level_offset_B(&sres->layout, level);
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@ -1358,9 +1363,6 @@ agx_cmdbuf(struct agx_device *dev, struct drm_asahi_cmd_render *c,
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unsigned stride_lines =
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sres->layout.compression_layer_stride_B / AIL_CACHELINE;
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c->stencil.comp_stride = (stride_lines - 1) << 14;
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zls_control.s_compress_1 = true;
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zls_control.s_compress_2 = true;
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}
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c->isp_bgobjvals |= clear_stencil;
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