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radv: support secure submission

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Set AMDGPU_IB_FLAGS_SECURE on IBs to support secure submission

Signed-off-by: Trigger Huang <Trigger.Huang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40619>
This commit is contained in:
Trigger Huang 2026-02-06 12:30:00 +08:00 • committed by Marge Bot
parent 535207a075
commit 540864685d
3 changed files with 12 additions and 2 deletions
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2
src/amd/vulkan/radv_queue.c
View file

@ -215,6 +215,7 @@ radv_queue_submit_empty(struct radv_queue *queue, struct vk_queue_submit *submis
struct radv_winsys_submit_info submit = {
.ip_type = radv_queue_ring(queue),
.queue_index = queue->vk.index_in_family,
.secure = submission->is_protected,
};
return device->ws->cs_submit(ctx, &submit, submission->wait_count, submission->waits, submission->signal_count,
@ -1713,6 +1714,7 @@ radv_queue_submit_normal(struct radv_queue *queue, struct vk_queue_submit *submi
.continue_preamble_cs = continue_preambles,
.postamble_cs = postambles,
.uses_shadow_regs = queue->state.uses_shadow_regs,
.secure = submission->is_protected,
};
for (uint32_t j = 0, advance; j < cmd_buffer_count; j += advance) {

1
src/amd/vulkan/radv_radeon_winsys.h
View file

@ -186,6 +186,7 @@ struct radv_winsys_submit_info {
struct ac_cmdbuf **continue_preamble_cs;
struct ac_cmdbuf **postamble_cs;
bool uses_shadow_regs;
bool secure;
};
/* Kernel effectively allows 0-31. This sets some priorities for fixed

11
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
View file

@ -999,7 +999,8 @@ radv_amdgpu_winsys_cs_submit_internal(struct radv_amdgpu_ctx *ctx, int queue_idx
struct ac_cmdbuf **cs_array, unsigned cs_count,
struct ac_cmdbuf **initial_preamble_cs, unsigned initial_preamble_count,
struct ac_cmdbuf **continue_preamble_cs, unsigned continue_preamble_count,
struct ac_cmdbuf **postamble_cs, unsigned postamble_count, bool uses_shadow_regs)
struct ac_cmdbuf **postamble_cs, unsigned postamble_count, bool uses_shadow_regs,
bool secure)
{
VkResult result;
@ -1055,6 +1056,9 @@ radv_amdgpu_winsys_cs_submit_internal(struct radv_amdgpu_ctx *ctx, int queue_idx
assert(cs->num_ib_buffers == 1);
ib = radv_amdgpu_cs_ib_to_info(cs, cs->ib_buffers[0]);
if (secure && ((ib.ip_type == AMDGPU_HW_IP_GFX) || (ib.ip_type == AMDGPU_HW_IP_DMA)))
ib.flags |= AMDGPU_IB_FLAGS_SECURE;
ibs[num_submitted_ibs++] = ib;
ibs_per_ip[cs->hw_ip]++;
}
@ -1107,6 +1111,9 @@ radv_amdgpu_winsys_cs_submit_internal(struct radv_amdgpu_ctx *ctx, int queue_idx
if (uses_shadow_regs && ib.ip_type == AMDGPU_HW_IP_GFX)
ib.flags |= AMDGPU_IB_FLAG_PREEMPT;
if (secure && ((ib.ip_type == AMDGPU_HW_IP_GFX) || (ib.ip_type == AMDGPU_HW_IP_DMA)))
ib.flags |= AMDGPU_IB_FLAGS_SECURE;
assert(num_submitted_ibs < ib_array_size);
ibs[num_submitted_ibs++] = ib;
ibs_per_ip[cs->hw_ip]++;
@ -1310,7 +1317,7 @@ radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx, const struct radv_w
result = radv_amdgpu_winsys_cs_submit_internal(
ctx, submit->queue_index, &sem_info, submit->cs_array, submit->cs_count, submit->initial_preamble_cs,
submit->initial_preamble_count, submit->continue_preamble_cs, submit->continue_preamble_count,
submit->postamble_cs, submit->postamble_count, submit->uses_shadow_regs);
submit->postamble_cs, submit->postamble_count, submit->uses_shadow_regs, submit->secure);
}
out: