From 5391e37b6b28aff307a3d83882ca44b94e3d4faa Mon Sep 17 00:00:00 2001
From: Sagar Ghuge <sagar.ghuge@intel.com>
Date: Thu, 28 Jan 2021 09:33:50 -0800
Subject: [PATCH] intel/genxml: Add new State Cache Perf Fix Disabled field

This patch adds new field to COMMON_SLICE_CHICKEN3 register.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39982>
---
 src/intel/genxml/gen110.xml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/intel/genxml/gen110.xml b/src/intel/genxml/gen110.xml
index 124f6af2454..74e5cfad259 100644
--- a/src/intel/genxml/gen110.xml
+++ b/src/intel/genxml/gen110.xml
@@ -3207,7 +3207,9 @@
   </register>
   <register name="COMMON_SLICE_CHICKEN3" length="1" num="0x7304">
     <field name="PS Thread Panic Dispatch" dword="0" bits="7:6" type="uint" />
+    <field name="State Cache Perf Fix Disabled" dword="0" bits="13:13" type="bool"/>
     <field name="PS Thread Panic Dispatch Mask" dword="0" bits="23:22" type="uint" />
+    <field name="State Cache Perf Fix Disabled Mask" dword="0" bits="29:29" type="bool"/>
   </register>
   <register name="COMMON_SLICE_CHICKEN4" length="1" num="0x7300">
     <field name="Enable Hardware Filtering in WM" dword="0" bits="5:5" type="bool" />