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brw: Fix EU validation of VxH and Vx1 region

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Use same approach as the other code checking for this vstride.  Argument
could be made we want to reuse the same enum value for both the encoded
and decoded version, but for now follow the existing practice.

This will cause
dEQP-VK.spirv_assembly.instruction.compute.untyped_pointers.vulkan_memory_model.type_punning.load.push_constant.int64_to_uint64
and similar tests to fail validation on BMG.  Later patch will fix that.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38125>
This commit is contained in:
Caio Oliveira 2025-10-28 16:06:10 -07:00 • committed by Marge Bot
parent 15924e941c
commit 538fd7266e
1 changed files with 1 additions and 1 deletions
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2
src/intel/compiler/brw/brw_eu_validate.c
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@ -1755,7 +1755,7 @@ special_requirements_for_handling_double_precision_data_types(
if (devinfo->verx10 >= 125 &&
(brw_type_is_float_or_bfloat(type) || brw_type_size_bytes(type) == 8)) {
ERROR_IF(address_mode == BRW_ADDRESS_REGISTER_INDIRECT_REGISTER &&
vstride == BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL,
vstride == STRIDE(BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL),
"Vx1 and VxH indirect addressing for Float, Half-Float, "
"Double-Float, Quad-Word, and Bfloat16 data must not be used");
}