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intel/brw: add load_msaa_rate_intel intrinsic

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Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Caleb Callaway <caleb.callaway@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38879>
This commit is contained in:
Iván Briano 2025-12-09 17:04:48 -08:00 • committed by Marge Bot
parent 3448f3ce4a
commit 5383afadbf
3 changed files with 11 additions and 0 deletions
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1
src/compiler/nir/nir_divergence_analysis.c
View file

@ -364,6 +364,7 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state)
case nir_intrinsic_load_call_return_address_amd:
case nir_intrinsic_load_indirect_address_intel:
case nir_intrinsic_load_alpha_to_coverage_enable_ir3:
case nir_intrinsic_load_msaa_rate_intel:
is_divergent = false;
break;

3
src/compiler/nir/nir_intrinsics.py
View file

@ -2653,6 +2653,9 @@ system_value("indirect_address_intel", 1)
# The semantics of it depend on the HW state.
system_value("coverage_mask_intel", 1)
# MSAA rate provided by the FS payload.
system_value("msaa_rate_intel", 1)
# Load a relocatable 32-bit value
intrinsic("load_reloc_const_intel", dest_comp=1, bit_sizes=[32],
indices=[PARAM_IDX, BASE], flags=[CAN_ELIMINATE, CAN_REORDER])

7
src/intel/compiler/brw/brw_from_nir.cpp
View file

@ -3813,6 +3813,13 @@ brw_from_nir_emit_fs_intrinsic(nir_to_brw_state &ntb,
break;
}
case nir_intrinsic_load_msaa_rate_intel: {
brw_reg msaa = brw_uw1_grf(1, 1);
dest.type = BRW_TYPE_UD;
bld.ADD(dest, bld.AND(msaa, brw_imm_uw(0xf)), brw_imm_ud(1));
break;
}
case nir_intrinsic_store_output: {
const brw_reg src = get_nir_src(ntb, instr->src[0], -1);
const nir_io_semantics sem = nir_intrinsic_io_semantics(instr);