From 5383afadbf58a7c3fdbe765b0fafabc5fa60dbf1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Iv=C3=A1n=20Briano?= Date: Tue, 9 Dec 2025 17:04:48 -0800 Subject: [PATCH] intel/brw: add load_msaa_rate_intel intrinsic Reviewed-by: Lionel Landwerlin Tested-by: Caleb Callaway Part-of: --- src/compiler/nir/nir_divergence_analysis.c | 1 + src/compiler/nir/nir_intrinsics.py | 3 +++ src/intel/compiler/brw/brw_from_nir.cpp | 7 +++++++ 3 files changed, 11 insertions(+) diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c index 31eddf5bebe..1536b065d51 100644 --- a/src/compiler/nir/nir_divergence_analysis.c +++ b/src/compiler/nir/nir_divergence_analysis.c @@ -364,6 +364,7 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state) case nir_intrinsic_load_call_return_address_amd: case nir_intrinsic_load_indirect_address_intel: case nir_intrinsic_load_alpha_to_coverage_enable_ir3: + case nir_intrinsic_load_msaa_rate_intel: is_divergent = false; break; diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index 3d157d99a0e..615f2699098 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -2653,6 +2653,9 @@ system_value("indirect_address_intel", 1) # The semantics of it depend on the HW state. system_value("coverage_mask_intel", 1) +# MSAA rate provided by the FS payload. +system_value("msaa_rate_intel", 1) + # Load a relocatable 32-bit value intrinsic("load_reloc_const_intel", dest_comp=1, bit_sizes=[32], indices=[PARAM_IDX, BASE], flags=[CAN_ELIMINATE, CAN_REORDER]) diff --git a/src/intel/compiler/brw/brw_from_nir.cpp b/src/intel/compiler/brw/brw_from_nir.cpp index 2d632077fb8..6106bacddbe 100644 --- a/src/intel/compiler/brw/brw_from_nir.cpp +++ b/src/intel/compiler/brw/brw_from_nir.cpp @@ -3813,6 +3813,13 @@ brw_from_nir_emit_fs_intrinsic(nir_to_brw_state &ntb, break; } + case nir_intrinsic_load_msaa_rate_intel: { + brw_reg msaa = brw_uw1_grf(1, 1); + dest.type = BRW_TYPE_UD; + bld.ADD(dest, bld.AND(msaa, brw_imm_uw(0xf)), brw_imm_ud(1)); + break; + } + case nir_intrinsic_store_output: { const brw_reg src = get_nir_src(ntb, instr->src[0], -1); const nir_io_semantics sem = nir_intrinsic_io_semantics(instr);