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freedreno/ir3: Do not allow 16-bit mad.x24

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Doesn't work with half registers. For 16-bit operations, there is mad.x16.

Cc: mesa-stable
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31334>
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David Heidelberg 2024-09-30 21:07:41 +09:00 • committed by Marge Bot
parent c36cc1fdf2
commit 51f04dc804
1 changed files with 9 additions and 0 deletions
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9
src/freedreno/ir3/ir3_validate.c
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@ -347,6 +347,15 @@ validate_instr(struct ir3_validate_ctx *ctx, struct ir3_instruction *instr)
break;
case 3:
switch (instr->opc) {
case OPC_MAD_S24:
case OPC_MAD_U24:
validate_assert(ctx, !(instr->dsts[0]->flags & IR3_REG_HALF));
validate_assert(ctx, !(instr->srcs[0]->flags & IR3_REG_HALF));
break;
default:
break;
}
/* Validate that cat3 opc matches the src type. We've already checked
* that all the src regs are same type
*/