From 51f04dc804262029cf32066ae24a8c66f8e36014 Mon Sep 17 00:00:00 2001
From: David Heidelberg <david@ixit.cz>
Date: Mon, 30 Sep 2024 21:07:41 +0900
Subject: [PATCH] freedreno/ir3: Do not allow 16-bit mad.x24

Doesn't work with half registers. For 16-bit operations, there is mad.x16.

Cc: mesa-stable
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31334>
---
 src/freedreno/ir3/ir3_validate.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/freedreno/ir3/ir3_validate.c b/src/freedreno/ir3/ir3_validate.c
index 914b8480b88..78f526366b8 100644
--- a/src/freedreno/ir3/ir3_validate.c
+++ b/src/freedreno/ir3/ir3_validate.c
@@ -347,6 +347,15 @@ validate_instr(struct ir3_validate_ctx *ctx, struct ir3_instruction *instr)
 
       break;
    case 3:
+      switch (instr->opc) {
+      case OPC_MAD_S24:
+      case OPC_MAD_U24:
+         validate_assert(ctx, !(instr->dsts[0]->flags & IR3_REG_HALF));
+         validate_assert(ctx, !(instr->srcs[0]->flags & IR3_REG_HALF));
+         break;
+      default:
+         break;
+      }
       /* Validate that cat3 opc matches the src type.  We've already checked
        * that all the src regs are same type
        */