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ac,radeonsi: add has_sqtt_auto_flush_mode_bug

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16303>
This commit is contained in:
Samuel Pitoiset 2022-05-03 17:18:09 +02:00 • committed by Marge Bot
parent 6f4b5fb675
commit 4f9ae10296
3 changed files with 6 additions and 1 deletions
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4
src/amd/common/ac_gpu_info.c
View file

@ -1252,6 +1252,9 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
util_bitcount(info->enabled_rb_mask) !=
info->max_render_backends;
/* On GFX10.3, the polarity of AUTO_FLUSH_MODE is inverted. */
info->has_sqtt_auto_flush_mode_bug = info->chip_class == GFX10_3;
info->max_sgpr_alloc = info->family == CHIP_TONGA || info->family == CHIP_ICELAND ? 96 : 104;
if (!info->has_graphics && info->family >= CHIP_ALDEBARAN) {
@ -1375,6 +1378,7 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f)
fprintf(f, " has_3d_cube_border_color_mipmap = %i\n", info->has_3d_cube_border_color_mipmap);
fprintf(f, " never_stop_sq_perf_counters = %i\n", info->never_stop_sq_perf_counters);
fprintf(f, " has_sqtt_rb_harvest_bug = %i\n", info->has_sqtt_rb_harvest_bug);
fprintf(f, " has_sqtt_auto_flush_mode_bug = %i\n", info->has_sqtt_auto_flush_mode_bug);
fprintf(f, "Display features:\n");
fprintf(f, " use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);

1
src/amd/common/ac_gpu_info.h
View file

@ -89,6 +89,7 @@ struct radeon_info {
bool has_3d_cube_border_color_mipmap;
bool never_stop_sq_perf_counters;
bool has_sqtt_rb_harvest_bug;
bool has_sqtt_auto_flush_mode_bug;
/* Display features. */
/* There are 2 display DCC codepaths, because display expects unaligned DCC. */

2
src/gallium/drivers/radeonsi/si_sqtt.c
View file

@ -140,7 +140,7 @@ si_emit_thread_trace_start(struct si_context* sctx,
S_008D1C_REG_DROP_ON_STALL(0) |
S_008D1C_LOWATER_OFFSET(
sctx->chip_class >= GFX10_3 ? 4 : 0) |
S_008D1C_AUTO_FLUSH_MODE(sctx->chip_class == GFX10_3));
S_008D1C_AUTO_FLUSH_MODE(sctx->screen->info.has_sqtt_auto_flush_mode_bug));
} else {
/* Order seems important for the following 4 registers. */
radeon_set_uconfig_reg(R_030CDC_SQ_THREAD_TRACE_BASE2,