diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 830e615fe2b..25a83b4f916 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -1252,6 +1252,9 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
                                    util_bitcount(info->enabled_rb_mask) !=
                                    info->max_render_backends;
 
+   /* On GFX10.3, the polarity of AUTO_FLUSH_MODE is inverted. */
+   info->has_sqtt_auto_flush_mode_bug = info->chip_class == GFX10_3;
+
    info->max_sgpr_alloc = info->family == CHIP_TONGA || info->family == CHIP_ICELAND ? 96 : 104;
 
    if (!info->has_graphics && info->family >= CHIP_ALDEBARAN) {
@@ -1375,6 +1378,7 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f)
    fprintf(f, "    has_3d_cube_border_color_mipmap = %i\n", info->has_3d_cube_border_color_mipmap);
    fprintf(f, "    never_stop_sq_perf_counters = %i\n", info->never_stop_sq_perf_counters);
    fprintf(f, "    has_sqtt_rb_harvest_bug = %i\n", info->has_sqtt_rb_harvest_bug);
+   fprintf(f, "    has_sqtt_auto_flush_mode_bug = %i\n", info->has_sqtt_auto_flush_mode_bug);
 
    fprintf(f, "Display features:\n");
    fprintf(f, "    use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 8abcd08ae57..8cd7a820580 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -89,6 +89,7 @@ struct radeon_info {
    bool has_3d_cube_border_color_mipmap;
    bool never_stop_sq_perf_counters;
    bool has_sqtt_rb_harvest_bug;
+   bool has_sqtt_auto_flush_mode_bug;
 
    /* Display features. */
    /* There are 2 display DCC codepaths, because display expects unaligned DCC. */
diff --git a/src/gallium/drivers/radeonsi/si_sqtt.c b/src/gallium/drivers/radeonsi/si_sqtt.c
index bb351f9b057..406f8e6121e 100644
--- a/src/gallium/drivers/radeonsi/si_sqtt.c
+++ b/src/gallium/drivers/radeonsi/si_sqtt.c
@@ -140,7 +140,7 @@ si_emit_thread_trace_start(struct si_context* sctx,
                                           S_008D1C_REG_DROP_ON_STALL(0) |
                                           S_008D1C_LOWATER_OFFSET(
                                              sctx->chip_class >= GFX10_3 ? 4 : 0) |
-                                          S_008D1C_AUTO_FLUSH_MODE(sctx->chip_class == GFX10_3));
+                                          S_008D1C_AUTO_FLUSH_MODE(sctx->screen->info.has_sqtt_auto_flush_mode_bug));
       } else {
          /* Order seems important for the following 4 registers. */
          radeon_set_uconfig_reg(R_030CDC_SQ_THREAD_TRACE_BASE2,