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iris: Set CS stall bit during HIZ_CCS_WT surface fast clear

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It make sense to enable CS stall so that it guarantees that the fast
clear will start after tile cache flush has completed.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23063>
This commit is contained in:
Sagar Ghuge 2023-05-16 14:39:12 -07:00
parent 688ee02864
commit 4f9314588f
1 changed files with 4 additions and 0 deletions
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4
src/gallium/drivers/iris/iris_clear.c
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@ -481,9 +481,13 @@ fast_clear_depth(struct iris_context *ice,
*
* There may have been a write to this depth buffer. Flush it from the
* tile cache just in case.
*
* Set CS stall bit to guarantee that the fast clear starts the execution
* after the tile cache flush completed.
*/
iris_emit_pipe_control_flush(batch, "hiz_ccs_wt: before fast clear",
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_TILE_CACHE_FLUSH);
}