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anv: Set CS stall bit during HIZ_CCS_WT surface fast clear

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It make sense to enable CS stall so that it guarantees that the fast
clear will start after tile cache flush has completed.

cc: mesa-stable
closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9030

Fixes: e488773b ("anv: Fast clear depth/stencil surface in vkCmdClearAttachments"
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23063>
This commit is contained in:
Sagar Ghuge 2023-05-16 11:25:33 -07:00
parent 241741a77a
commit 688ee02864
1 changed files with 4 additions and 0 deletions
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4
src/intel/vulkan/anv_blorp.c
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@ -1520,9 +1520,13 @@ anv_fast_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer,
*
* There may have been a write to this depth buffer. Flush it from the
* tile cache just in case.
*
* Set CS stall bit to guarantee that the fast clear starts the execution
* after the tile cache flush completed.
*/
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_DEPTH_CACHE_FLUSH_BIT |
ANV_PIPE_CS_STALL_BIT |
ANV_PIPE_TILE_CACHE_FLUSH_BIT,
"before clear hiz_ccs_wt");
}